Struct stm32g0::stm32g0c1::usart1::cr2::CPOL_W

pub struct CPOL_W<'a> { /* fields omitted */ }

Field CPOL writer - Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .

Implementations

impl<'a> CPOL_W<'a>

pub fn variant(self, variant: CPOL_A) -> &'a mut W

Writes variant to the field

pub fn b_0x0(self) -> &'a mut W

Steady low value on SCLK pin outside transmission window

pub fn b_0x1(self) -> &'a mut W

Steady high value on SCLK pin outside transmission window

pub fn set_bit(self) -> &'a mut W

Sets the field bit

pub fn clear_bit(self) -> &'a mut W

Clears the field bit

pub fn bit(self, value: bool) -> &'a mut W

Writes raw bits to the field