Struct stm32g0::stm32g0c1::usart1::cr2::CPHA_W

pub struct CPHA_W<'a> { /* fields omitted */ }

Field CPHA writer - Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to .

Implementations

impl<'a> CPHA_W<'a>

pub fn variant(self, variant: CPHA_A) -> &'a mut W

Writes variant to the field

pub fn b_0x0(self) -> &'a mut W

The first clock transition is the first data capture edge

pub fn b_0x1(self) -> &'a mut W

The second clock transition is the first data capture edge

pub fn set_bit(self) -> &'a mut W

Sets the field bit

pub fn clear_bit(self) -> &'a mut W

Clears the field bit

pub fn bit(self, value: bool) -> &'a mut W

Writes raw bits to the field