Struct stm32g0::stm32g0c1::tim15::sr::UIF_W

pub struct UIF_W<'a> { /* fields omitted */ }

Field UIF writer - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.

Implementations

impl<'a> UIF_W<'a>

pub fn variant(self, variant: UIF_A) -> &'a mut W

Writes variant to the field

pub fn b_0x0(self) -> &'a mut W

No update occurred.

pub fn b_0x1(self) -> &'a mut W

Update interrupt pending. This bit is set by hardware when the registers are updated:

pub fn set_bit(self) -> &'a mut W

Sets the field bit

pub fn clear_bit(self) -> &'a mut W

Clears the field bit

pub fn bit(self, value: bool) -> &'a mut W

Writes raw bits to the field