Struct stm32g0::stm32g0c1::tim15::sr::CC1IF_W

pub struct CC1IF_W<'a> { /* fields omitted */ }

Field CC1IF writer - Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).

Implementations

impl<'a> CC1IF_W<'a>

pub fn variant(self, variant: CC1IF_A) -> &'a mut W

Writes variant to the field

pub fn b_0x0(self) -> &'a mut W

No compare match / No input capture occurred

pub fn b_0x1(self) -> &'a mut W

A compare match or an input capture occurred

pub fn set_bit(self) -> &'a mut W

Sets the field bit

pub fn clear_bit(self) -> &'a mut W

Clears the field bit

pub fn bit(self, value: bool) -> &'a mut W

Writes raw bits to the field