Struct stm32g0::stm32g0b0::tim3::sr::UIF_W [−][src]
pub struct UIF_W<'a> { /* fields omitted */ }
Expand description
Field UIF
writer - Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.
Implementations
Update interrupt pending. This bit is set by hardware when the registers are updated: