Struct stm32g0::stm32g0b0::tim16::ccmr1_output::OC1PE_W

pub struct OC1PE_W<'a> { /* fields omitted */ }

Field OC1PE writer - Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Implementations

impl<'a> OC1PE_W<'a>

pub fn variant(self, variant: OC1PE_A) -> &'a mut W

Writes variant to the field

pub fn b_0x0(self) -> &'a mut W

Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.

pub fn b_0x1(self) -> &'a mut W

Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.

pub fn set_bit(self) -> &'a mut W

Sets the field bit

pub fn clear_bit(self) -> &'a mut W

Clears the field bit

pub fn bit(self, value: bool) -> &'a mut W

Writes raw bits to the field