Struct stm32g0::stm32g0b0::tim15::ccmr1_output::R

pub struct R(_);

Register CCMR1_Output reader

Implementations

impl R

pub fn cc1s(&self) -> CC1S_R

Bits 0:1 - Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in TIMx_CCER).

pub fn oc1fe(&self) -> OC1FE_R

Bit 2 - Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.

pub fn oc1pe(&self) -> OC1PE_R

Bit 3 - Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

pub fn oc1m1(&self) -> OC1M1_R

Bits 4:6 - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16.

pub fn cc2s(&self) -> CC2S_R

Bits 8:9 - Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in TIMx_CCER).

pub fn oc2fe(&self) -> OC2FE_R

Bit 10 - Output Compare 2 fast enable

pub fn oc2pe(&self) -> OC2PE_R

Bit 11 - Output Compare 2 preload enable

pub fn oc2m(&self) -> OC2M_R

Bits 12:14 - Output Compare 2 mode

pub fn oc1m2(&self) -> OC1M2_R

Bit 16 - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16.

pub fn oc2m_3(&self) -> OC2M_3_R

Bit 24 - Output Compare 2 mode

Methods from Deref<Target = R<CCMR1_OUTPUT_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CCMR1_OUTPUT_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CCMR1_OUTPUT_SPEC>> for R

fn from(reader: R<CCMR1_OUTPUT_SPEC>) -> Self

Performs the conversion.