Struct stm32g0::stm32g0b0::tim14::cr1::R [−][src]
pub struct R(_);
Expand description
Register CR1
reader
Implementations
Bit 0 - Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
Bit 1 - Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values.
Bit 2 - Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit
Bits 8:9 - Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),
Bit 11 - UIF status bit remapping