Struct stm32g0::stm32g0b0::tim1::cr2::W [−][src]
pub struct W(_);
Expand description
Register CR2
writer
Implementations
Bit 0 - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
Bit 2 - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
Bits 4:6 - Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
Bit 8 - Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Bit 9 - Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Bit 10 - Output Idle state 2 (OC2 output) Refer to OIS1 bit
Bit 11 - Output Idle state 2 (OC2N output) Refer to OIS1N bit
Bit 12 - Output Idle state 3 (OC3 output) Refer to OIS1 bit
Bit 13 - Output Idle state 3 (OC3N output) Refer to OIS1N bit
Bit 14 - Output Idle state 4 (OC4 output) Refer to OIS1 bit
Bit 16 - Output Idle state 5 (OC5 output) Refer to OIS1 bit
Bit 18 - Output Idle state 6 (OC6 output) Refer to OIS1 bit
Bits 20:23 - Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.