Struct stm32g0::stm32g041::rcc::pllsyscfgr::W [−][src]
pub struct W(_);
Expand description
Register PLLSYSCFGR
writer
Implementations
Bits 4:6 - Division factor M of the PLL input clock divider
Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output
Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output
Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output
Methods from Deref<Target = W<PLLSYSCFGR_SPEC>>
Trait Implementations
Performs the conversion.