Struct stm32g0::stm32g031::rcc::RegisterBlock[−][src]

#[repr(C)]pub struct RegisterBlock {
    pub cr: CR,
    pub icscr: ICSCR,
    pub cfgr: CFGR,
    pub pllsyscfgr: PLLSYSCFGR,
    pub cier: CIER,
    pub cifr: CIFR,
    pub cicr: CICR,
    pub ioprstr: IOPRSTR,
    pub ahbrstr: AHBRSTR,
    pub apbrstr1: APBRSTR1,
    pub apbrstr2: APBRSTR2,
    pub iopenr: IOPENR,
    pub ahbenr: AHBENR,
    pub apbenr1: APBENR1,
    pub apbenr2: APBENR2,
    pub iopsmenr: IOPSMENR,
    pub ahbsmenr: AHBSMENR,
    pub apbsmenr1: APBSMENR1,
    pub apbsmenr2: APBSMENR2,
    pub ccipr: CCIPR,
    pub bdcr: BDCR,
    pub csr: CSR,
    // some fields omitted
}

Register block

Fields

cr: CR

0x00 - Clock control register

icscr: ICSCR

0x04 - Internal clock sources calibration register

cfgr: CFGR

0x08 - Clock configuration register

pllsyscfgr: PLLSYSCFGR

0x0c - PLL configuration register

cier: CIER

0x18 - Clock interrupt enable register

cifr: CIFR

0x1c - Clock interrupt flag register

cicr: CICR

0x20 - Clock interrupt clear register

ioprstr: IOPRSTR

0x24 - GPIO reset register

ahbrstr: AHBRSTR

0x28 - AHB peripheral reset register

apbrstr1: APBRSTR1

0x2c - APB peripheral reset register 1

apbrstr2: APBRSTR2

0x30 - APB peripheral reset register 2

iopenr: IOPENR

0x34 - GPIO clock enable register

ahbenr: AHBENR

0x38 - AHB peripheral clock enable register

apbenr1: APBENR1

0x3c - APB peripheral clock enable register 1

apbenr2: APBENR2

0x40 - APB peripheral clock enable register 2

iopsmenr: IOPSMENR

0x44 - GPIO in Sleep mode clock enable register

ahbsmenr: AHBSMENR

0x48 - AHB peripheral clock enable in Sleep mode register

apbsmenr1: APBSMENR1

0x4c - APB peripheral clock enable in Sleep mode register 1

apbsmenr2: APBSMENR2

0x50 - APB peripheral clock enable in Sleep mode register 2

ccipr: CCIPR

0x54 - Peripherals independent clock configuration register

bdcr: BDCR

0x5c - RTC domain control register

csr: CSR

0x60 - Control/status register

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