Module cr1

SPI control register 1

Structs

CR1rs

SPI control register 1

Enums

BIDIMODE

Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode.

BIDIOE

Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode.

BR

Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode.

CPHA

Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.

CPOL

Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.

CRCEN

Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. This bit is not used in I2S mode.

CRCL

CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. This bit is not used in I2S mode.

CRCNEXT

Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI_DR register. This bit is not used in I2S mode.

LSBFIRST

Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode.

MSTR

Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode.

RXONLY

Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode.

SPE

SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page1021. This bit is not used in I2S mode.

SSI

Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode.

SSM

Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode.

Type Aliases

BIDIMODE_R

Field BIDIMODE reader - Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode.

BIDIMODE_W

Field BIDIMODE writer - Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode.

BIDIOE_R

Field BIDIOE reader - Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode.

BIDIOE_W

Field BIDIOE writer - Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode.

BR_R

Field BR reader - Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode.

BR_W

Field BR writer - Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode.

CPHA_R

Field CPHA reader - Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.

CPHA_W

Field CPHA writer - Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.

CPOL_R

Field CPOL reader - Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.

CPOL_W

Field CPOL writer - Clock polarity Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode.

CRCEN_R

Field CRCEN reader - Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. This bit is not used in I2S mode.

CRCEN_W

Field CRCEN writer - Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. This bit is not used in I2S mode.

CRCL_R

Field CRCL reader - CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. This bit is not used in I2S mode.

CRCL_W

Field CRCL writer - CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation. This bit is not used in I2S mode.

CRCNEXT_R

Field CRCNEXT reader - Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI_DR register. This bit is not used in I2S mode.

CRCNEXT_W

Field CRCNEXT writer - Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI_DR register. This bit is not used in I2S mode.

LSBFIRST_R

Field LSBFIRST reader - Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode.

LSBFIRST_W

Field LSBFIRST writer - Frame format Note: 1. This bit should not be changed when communication is ongoing. 2. This bit is not used in I2S mode and SPI TI mode.

MSTR_R

Field MSTR reader - Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode.

MSTR_W

Field MSTR writer - Master selection Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode.

R

Register CR1 reader

RXONLY_R

Field RXONLY reader - Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode.

RXONLY_W

Field RXONLY writer - Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode.

SPE_R

Field SPE reader - SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page1021. This bit is not used in I2S mode.

SPE_W

Field SPE writer - SPI enable Note: When disabling the SPI, follow the procedure described in SPI on page1021. This bit is not used in I2S mode.

SSI_R

Field SSI reader - Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode.

SSI_W

Field SSI writer - Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I2S mode and SPI TI mode.

SSM_R

Field SSM reader - Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode.

SSM_W

Field SSM writer - Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I2S mode and SPI TI mode.

W

Register CR1 writer