Expand description
Low-power universal asynchronous receiver transmitter
Modules§
- brr
- LPUART baud rate register
- cr2
- LPUART control register 2
- cr3
- LPUART control register 3
- cr1_
disabled - LPUART control register 1 [alternate]
- cr1_
enabled - LPUART control register 1 [alternate]
- icr
- LPUART interrupt flag clear register
- isr_
disabled - LPUART interrupt and status register [alternate]
- isr_
enabled - LPUART interrupt and status register [alternate]
- presc
- LPUART prescaler register
- rdr
- LPUART receive data register
- rqr
- LPUART request register
- tdr
- LPUART transmit data register
Structs§
- Register
Block - Register block
Type Aliases§
- BRR
- BRR (rw) register accessor: LPUART baud rate register
- CR2
- CR2 (rw) register accessor: LPUART control register 2
- CR3
- CR3 (rw) register accessor: LPUART control register 3
- CR1_
DISABLED - CR1_disabled (rw) register accessor: LPUART control register 1 [alternate]
- CR1_
ENABLED - CR1_enabled (rw) register accessor: LPUART control register 1 [alternate]
- ICR
- ICR (w) register accessor: LPUART interrupt flag clear register
- ISR_
DISABLED - ISR_disabled (r) register accessor: LPUART interrupt and status register [alternate]
- ISR_
ENABLED - ISR_enabled (r) register accessor: LPUART interrupt and status register [alternate]
- PRESC
- PRESC (rw) register accessor: LPUART prescaler register
- RDR
- RDR (r) register accessor: LPUART receive data register
- RQR
- RQR (w) register accessor: LPUART request register
- TDR
- TDR (rw) register accessor: LPUART transmit data register