Module cr1

control register 1

Structs

CR1rs

control register 1

Enums

ARPE

Auto-reload preload enable

CEN

Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.

CKD

Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),

CMS

Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)

DIR

Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.

OPM

One-pulse mode

UDIS

Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.

URS

Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller

Type Aliases

ARPE_R

Field ARPE reader - Auto-reload preload enable

ARPE_W

Field ARPE writer - Auto-reload preload enable

CEN_R

Field CEN reader - Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.

CEN_W

Field CEN writer - Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.

CKD_R

Field CKD reader - Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),

CKD_W

Field CKD writer - Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),

CMS_R

Field CMS reader - Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)

CMS_W

Field CMS writer - Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)

DIR_R

Field DIR reader - Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.

DIR_W

Field DIR writer - Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.

OPM_R

Field OPM reader - One-pulse mode

OPM_W

Field OPM writer - One-pulse mode

R

Register CR1 reader

UDIS_R

Field UDIS reader - Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.

UDIS_W

Field UDIS writer - Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.

UIFREMAP_R

Field UIFREMAP reader - UIF status bit remapping

UIFREMAP_W

Field UIFREMAP writer - UIF status bit remapping

URS_R

Field URS reader - Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller

URS_W

Field URS writer - Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller

W

Register CR1 writer