stm32g0_staging/stm32g0c1/
tim3.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved_7_ccmr2: [u8; 0x04],
13    ccer: CCER,
14    _reserved_9_cnt: [u8; 0x04],
15    psc: PSC,
16    arr: ARR,
17    _reserved12: [u8; 0x04],
18    ccr: [CCR; 4],
19    _reserved13: [u8; 0x04],
20    dcr: DCR,
21    dmar: DMAR,
22    or1: OR1,
23    _reserved16: [u8; 0x0c],
24    af1: AF1,
25    _reserved17: [u8; 0x04],
26    tisel: TISEL,
27}
28impl RegisterBlock {
29    ///0x00 - control register 1
30    #[inline(always)]
31    pub const fn cr1(&self) -> &CR1 {
32        &self.cr1
33    }
34    ///0x04 - control register 2
35    #[inline(always)]
36    pub const fn cr2(&self) -> &CR2 {
37        &self.cr2
38    }
39    ///0x08 - slave mode control register
40    #[inline(always)]
41    pub const fn smcr(&self) -> &SMCR {
42        &self.smcr
43    }
44    ///0x0c - DMA/Interrupt enable register
45    #[inline(always)]
46    pub const fn dier(&self) -> &DIER {
47        &self.dier
48    }
49    ///0x10 - status register
50    #[inline(always)]
51    pub const fn sr(&self) -> &SR {
52        &self.sr
53    }
54    ///0x14 - event generation register
55    #[inline(always)]
56    pub const fn egr(&self) -> &EGR {
57        &self.egr
58    }
59    ///0x18 - capture/compare mode register 1 (input mode)
60    #[inline(always)]
61    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
62        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
63    }
64    ///0x18 - capture/compare mode register 1 (output mode)
65    #[inline(always)]
66    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
67        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
68    }
69    ///0x1c - capture/compare mode register 2 (input mode)
70    #[inline(always)]
71    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
72        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
73    }
74    ///0x1c - capture/compare mode register 2 (output mode)
75    #[inline(always)]
76    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
77        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
78    }
79    ///0x20 - capture/compare enable register
80    #[inline(always)]
81    pub const fn ccer(&self) -> &CCER {
82        &self.ccer
83    }
84    ///0x24 - counter
85    #[inline(always)]
86    pub const fn cnt_alternate5(&self) -> &CNT_ALTERNATE5 {
87        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).cast() }
88    }
89    ///0x24 - counter
90    #[inline(always)]
91    pub const fn cnt(&self) -> &CNT {
92        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).cast() }
93    }
94    ///0x28 - prescaler
95    #[inline(always)]
96    pub const fn psc(&self) -> &PSC {
97        &self.psc
98    }
99    ///0x2c - auto-reload register
100    #[inline(always)]
101    pub const fn arr(&self) -> &ARR {
102        &self.arr
103    }
104    ///0x34..0x44 - capture/compare register
105    ///
106    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
107    #[inline(always)]
108    pub const fn ccr(&self, n: usize) -> &CCR {
109        &self.ccr[n]
110    }
111    ///Iterator for array of:
112    ///0x34..0x44 - capture/compare register
113    #[inline(always)]
114    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
115        self.ccr.iter()
116    }
117    ///0x34 - capture/compare register
118    #[inline(always)]
119    pub const fn ccr1(&self) -> &CCR {
120        self.ccr(0)
121    }
122    ///0x38 - capture/compare register
123    #[inline(always)]
124    pub const fn ccr2(&self) -> &CCR {
125        self.ccr(1)
126    }
127    ///0x3c - capture/compare register
128    #[inline(always)]
129    pub const fn ccr3(&self) -> &CCR {
130        self.ccr(2)
131    }
132    ///0x40 - capture/compare register
133    #[inline(always)]
134    pub const fn ccr4(&self) -> &CCR {
135        self.ccr(3)
136    }
137    ///0x48 - DMA control register
138    #[inline(always)]
139    pub const fn dcr(&self) -> &DCR {
140        &self.dcr
141    }
142    ///0x4c - DMA address for full transfer
143    #[inline(always)]
144    pub const fn dmar(&self) -> &DMAR {
145        &self.dmar
146    }
147    ///0x50 - TIM option register
148    #[inline(always)]
149    pub const fn or1(&self) -> &OR1 {
150        &self.or1
151    }
152    ///0x60 - TIM alternate function option register 1
153    #[inline(always)]
154    pub const fn af1(&self) -> &AF1 {
155        &self.af1
156    }
157    ///0x68 - TIM alternate function option register 1
158    #[inline(always)]
159    pub const fn tisel(&self) -> &TISEL {
160        &self.tisel
161    }
162}
163/**CR1 (rw) register accessor: control register 1
164
165You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
166
167See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:CR1)
168
169For information about available fields see [`mod@cr1`]
170module*/
171pub type CR1 = crate::Reg<cr1::CR1rs>;
172///control register 1
173pub mod cr1;
174/**CR2 (rw) register accessor: control register 2
175
176You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
177
178See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:CR2)
179
180For information about available fields see [`mod@cr2`]
181module*/
182pub type CR2 = crate::Reg<cr2::CR2rs>;
183///control register 2
184pub mod cr2;
185/**SMCR (rw) register accessor: slave mode control register
186
187You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
188
189See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:SMCR)
190
191For information about available fields see [`mod@smcr`]
192module*/
193pub type SMCR = crate::Reg<smcr::SMCRrs>;
194///slave mode control register
195pub mod smcr;
196/**DIER (rw) register accessor: DMA/Interrupt enable register
197
198You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
199
200See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:DIER)
201
202For information about available fields see [`mod@dier`]
203module*/
204pub type DIER = crate::Reg<dier::DIERrs>;
205///DMA/Interrupt enable register
206pub mod dier;
207/**SR (rw) register accessor: status register
208
209You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
210
211See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:SR)
212
213For information about available fields see [`mod@sr`]
214module*/
215pub type SR = crate::Reg<sr::SRrs>;
216///status register
217pub mod sr;
218/**EGR (w) register accessor: event generation register
219
220You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
221
222See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:EGR)
223
224For information about available fields see [`mod@egr`]
225module*/
226pub type EGR = crate::Reg<egr::EGRrs>;
227///event generation register
228pub mod egr;
229/**CCMR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)
230
231You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
232
233See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:CCMR1_Output)
234
235For information about available fields see [`mod@ccmr1_output`]
236module*/
237#[doc(alias = "CCMR1_Output")]
238pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
239///capture/compare mode register 1 (output mode)
240pub mod ccmr1_output;
241/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
242
243You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
244
245See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:CCMR1_Input)
246
247For information about available fields see [`mod@ccmr1_input`]
248module*/
249#[doc(alias = "CCMR1_Input")]
250pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
251///capture/compare mode register 1 (input mode)
252pub mod ccmr1_input;
253/**CCMR2_Output (rw) register accessor: capture/compare mode register 2 (output mode)
254
255You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
256
257See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:CCMR2_Output)
258
259For information about available fields see [`mod@ccmr2_output`]
260module*/
261#[doc(alias = "CCMR2_Output")]
262pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUTrs>;
263///capture/compare mode register 2 (output mode)
264pub mod ccmr2_output;
265/**CCMR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)
266
267You can [`read`](crate::Reg::read) this register and get [`ccmr2_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
268
269See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:CCMR2_Input)
270
271For information about available fields see [`mod@ccmr2_input`]
272module*/
273#[doc(alias = "CCMR2_Input")]
274pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUTrs>;
275///capture/compare mode register 2 (input mode)
276pub mod ccmr2_input;
277/**CCER (rw) register accessor: capture/compare enable register
278
279You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
280
281See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:CCER)
282
283For information about available fields see [`mod@ccer`]
284module*/
285pub type CCER = crate::Reg<ccer::CCERrs>;
286///capture/compare enable register
287pub mod ccer;
288/**CNT (rw) register accessor: counter
289
290You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
291
292See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:CNT)
293
294For information about available fields see [`mod@cnt`]
295module*/
296pub type CNT = crate::Reg<cnt::CNTrs>;
297///counter
298pub mod cnt;
299/**CNT_ALTERNATE5 (rw) register accessor: counter
300
301You can [`read`](crate::Reg::read) this register and get [`cnt_alternate5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt_alternate5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
302
303See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:CNT_ALTERNATE5)
304
305For information about available fields see [`mod@cnt_alternate5`]
306module*/
307pub type CNT_ALTERNATE5 = crate::Reg<cnt_alternate5::CNT_ALTERNATE5rs>;
308///counter
309pub mod cnt_alternate5;
310/**PSC (rw) register accessor: prescaler
311
312You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
313
314See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:PSC)
315
316For information about available fields see [`mod@psc`]
317module*/
318pub type PSC = crate::Reg<psc::PSCrs>;
319///prescaler
320pub mod psc;
321/**ARR (rw) register accessor: auto-reload register
322
323You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
324
325See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:ARR)
326
327For information about available fields see [`mod@arr`]
328module*/
329pub type ARR = crate::Reg<arr::ARRrs>;
330///auto-reload register
331pub mod arr;
332/**CCR (rw) register accessor: capture/compare register
333
334You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
335
336See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:CCR[1])
337
338For information about available fields see [`mod@ccr`]
339module*/
340pub type CCR = crate::Reg<ccr::CCRrs>;
341///capture/compare register
342pub mod ccr;
343/**DCR (rw) register accessor: DMA control register
344
345You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
346
347See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:DCR)
348
349For information about available fields see [`mod@dcr`]
350module*/
351pub type DCR = crate::Reg<dcr::DCRrs>;
352///DMA control register
353pub mod dcr;
354/**DMAR (rw) register accessor: DMA address for full transfer
355
356You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
357
358See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:DMAR)
359
360For information about available fields see [`mod@dmar`]
361module*/
362pub type DMAR = crate::Reg<dmar::DMARrs>;
363///DMA address for full transfer
364pub mod dmar;
365/**OR1 (rw) register accessor: TIM option register
366
367You can [`read`](crate::Reg::read) this register and get [`or1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
368
369See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:OR1)
370
371For information about available fields see [`mod@or1`]
372module*/
373pub type OR1 = crate::Reg<or1::OR1rs>;
374///TIM option register
375pub mod or1;
376/**AF1 (rw) register accessor: TIM alternate function option register 1
377
378You can [`read`](crate::Reg::read) this register and get [`af1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`af1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
379
380See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:AF1)
381
382For information about available fields see [`mod@af1`]
383module*/
384pub type AF1 = crate::Reg<af1::AF1rs>;
385///TIM alternate function option register 1
386pub mod af1;
387/**TISEL (rw) register accessor: TIM alternate function option register 1
388
389You can [`read`](crate::Reg::read) this register and get [`tisel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
390
391See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM3:TISEL)
392
393For information about available fields see [`mod@tisel`]
394module*/
395pub type TISEL = crate::Reg<tisel::TISELrs>;
396///TIM alternate function option register 1
397pub mod tisel;
stm32g0_staging/stm32g0c1/tim3.rs

stm32g0_staging/stm32g0c1/
tim3.rs
