stm32g0_staging/stm32g0c1/
tim14.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    _reserved1: [u8; 0x08],
7    dier: DIER,
8    sr: SR,
9    egr: EGR,
10    _reserved_4_ccmr1: [u8; 0x04],
11    _reserved5: [u8; 0x04],
12    ccer: CCER,
13    cnt: CNT,
14    psc: PSC,
15    arr: ARR,
16    _reserved9: [u8; 0x04],
17    ccr: [CCR; 1],
18    _reserved10: [u8; 0x30],
19    tisel: TISEL,
20}
21impl RegisterBlock {
22    ///0x00 - control register 1
23    #[inline(always)]
24    pub const fn cr1(&self) -> &CR1 {
25        &self.cr1
26    }
27    ///0x0c - DMA/Interrupt enable register
28    #[inline(always)]
29    pub const fn dier(&self) -> &DIER {
30        &self.dier
31    }
32    ///0x10 - status register
33    #[inline(always)]
34    pub const fn sr(&self) -> &SR {
35        &self.sr
36    }
37    ///0x14 - event generation register
38    #[inline(always)]
39    pub const fn egr(&self) -> &EGR {
40        &self.egr
41    }
42    ///0x18 - capture/compare mode register 1 (input mode)
43    #[inline(always)]
44    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
45        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
46    }
47    ///0x18 - capture/compare mode register 1 (output mode)
48    #[inline(always)]
49    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
50        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
51    }
52    ///0x20 - capture/compare enable register
53    #[inline(always)]
54    pub const fn ccer(&self) -> &CCER {
55        &self.ccer
56    }
57    ///0x24 - counter
58    #[inline(always)]
59    pub const fn cnt(&self) -> &CNT {
60        &self.cnt
61    }
62    ///0x28 - prescaler
63    #[inline(always)]
64    pub const fn psc(&self) -> &PSC {
65        &self.psc
66    }
67    ///0x2c - auto-reload register
68    #[inline(always)]
69    pub const fn arr(&self) -> &ARR {
70        &self.arr
71    }
72    ///0x34 - capture/compare register
73    ///
74    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
75    #[inline(always)]
76    pub const fn ccr(&self, n: usize) -> &CCR {
77        &self.ccr[n]
78    }
79    ///Iterator for array of:
80    ///0x34 - capture/compare register
81    #[inline(always)]
82    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
83        self.ccr.iter()
84    }
85    ///0x34 - capture/compare register
86    #[inline(always)]
87    pub const fn ccr1(&self) -> &CCR {
88        self.ccr(0)
89    }
90    ///0x68 - TIM timer input selection register
91    #[inline(always)]
92    pub const fn tisel(&self) -> &TISEL {
93        &self.tisel
94    }
95}
96/**CR1 (rw) register accessor: control register 1
97
98You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
99
100See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:CR1)
101
102For information about available fields see [`mod@cr1`]
103module*/
104pub type CR1 = crate::Reg<cr1::CR1rs>;
105///control register 1
106pub mod cr1;
107/**DIER (rw) register accessor: DMA/Interrupt enable register
108
109You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
110
111See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:DIER)
112
113For information about available fields see [`mod@dier`]
114module*/
115pub type DIER = crate::Reg<dier::DIERrs>;
116///DMA/Interrupt enable register
117pub mod dier;
118/**SR (rw) register accessor: status register
119
120You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
121
122See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:SR)
123
124For information about available fields see [`mod@sr`]
125module*/
126pub type SR = crate::Reg<sr::SRrs>;
127///status register
128pub mod sr;
129/**EGR (w) register accessor: event generation register
130
131You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
132
133See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:EGR)
134
135For information about available fields see [`mod@egr`]
136module*/
137pub type EGR = crate::Reg<egr::EGRrs>;
138///event generation register
139pub mod egr;
140/**CCMR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)
141
142You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:CCMR1_Output)
145
146For information about available fields see [`mod@ccmr1_output`]
147module*/
148#[doc(alias = "CCMR1_Output")]
149pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
150///capture/compare mode register 1 (output mode)
151pub mod ccmr1_output;
152/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
153
154You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
155
156See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:CCMR1_Input)
157
158For information about available fields see [`mod@ccmr1_input`]
159module*/
160#[doc(alias = "CCMR1_Input")]
161pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
162///capture/compare mode register 1 (input mode)
163pub mod ccmr1_input;
164/**CCER (rw) register accessor: capture/compare enable register
165
166You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:CCER)
169
170For information about available fields see [`mod@ccer`]
171module*/
172pub type CCER = crate::Reg<ccer::CCERrs>;
173///capture/compare enable register
174pub mod ccer;
175/**CNT (rw) register accessor: counter
176
177You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
178
179See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:CNT)
180
181For information about available fields see [`mod@cnt`]
182module*/
183pub type CNT = crate::Reg<cnt::CNTrs>;
184///counter
185pub mod cnt;
186/**PSC (rw) register accessor: prescaler
187
188You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
189
190See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:PSC)
191
192For information about available fields see [`mod@psc`]
193module*/
194pub type PSC = crate::Reg<psc::PSCrs>;
195///prescaler
196pub mod psc;
197/**ARR (rw) register accessor: auto-reload register
198
199You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
200
201See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:ARR)
202
203For information about available fields see [`mod@arr`]
204module*/
205pub type ARR = crate::Reg<arr::ARRrs>;
206///auto-reload register
207pub mod arr;
208/**CCR (rw) register accessor: capture/compare register
209
210You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
211
212See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:CCR[1])
213
214For information about available fields see [`mod@ccr`]
215module*/
216pub type CCR = crate::Reg<ccr::CCRrs>;
217///capture/compare register
218pub mod ccr;
219/**TISEL (rw) register accessor: TIM timer input selection register
220
221You can [`read`](crate::Reg::read) this register and get [`tisel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
222
223See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM14:TISEL)
224
225For information about available fields see [`mod@tisel`]
226module*/
227pub type TISEL = crate::Reg<tisel::TISELrs>;
228///TIM timer input selection register
229pub mod tisel;
stm32g0_staging/stm32g0c1/tim14.rs

stm32g0_staging/stm32g0c1/
tim14.rs
