stm32g0_staging/stm32g0c1/
tim1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved_7_ccmr2: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    rcr: RCR,
18    ccr: [CCR; 4],
19    bdtr: BDTR,
20    dcr: DCR,
21    dmar: DMAR,
22    or1: OR1,
23    ccmr3_output: CCMR3_OUTPUT,
24    ccr5: CCR5,
25    ccr6: CCR6,
26    af1: AF1,
27    af2: AF2,
28    tisel: TISEL,
29}
30impl RegisterBlock {
31    ///0x00 - control register 1
32    #[inline(always)]
33    pub const fn cr1(&self) -> &CR1 {
34        &self.cr1
35    }
36    ///0x04 - control register 2
37    #[inline(always)]
38    pub const fn cr2(&self) -> &CR2 {
39        &self.cr2
40    }
41    ///0x08 - slave mode control register
42    #[inline(always)]
43    pub const fn smcr(&self) -> &SMCR {
44        &self.smcr
45    }
46    ///0x0c - DMA/Interrupt enable register
47    #[inline(always)]
48    pub const fn dier(&self) -> &DIER {
49        &self.dier
50    }
51    ///0x10 - status register
52    #[inline(always)]
53    pub const fn sr(&self) -> &SR {
54        &self.sr
55    }
56    ///0x14 - event generation register
57    #[inline(always)]
58    pub const fn egr(&self) -> &EGR {
59        &self.egr
60    }
61    ///0x18 - capture/compare mode register 1 (output mode)
62    #[inline(always)]
63    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
64        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
65    }
66    ///0x18 - capture/compare mode register 1 (output mode)
67    #[inline(always)]
68    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
69        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
70    }
71    ///0x1c - capture/compare mode register 2 (output mode)
72    #[inline(always)]
73    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
74        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
75    }
76    ///0x1c - capture/compare mode register 2 (output mode)
77    #[inline(always)]
78    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
79        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
80    }
81    ///0x20 - capture/compare enable register
82    #[inline(always)]
83    pub const fn ccer(&self) -> &CCER {
84        &self.ccer
85    }
86    ///0x24 - counter
87    #[inline(always)]
88    pub const fn cnt(&self) -> &CNT {
89        &self.cnt
90    }
91    ///0x28 - prescaler
92    #[inline(always)]
93    pub const fn psc(&self) -> &PSC {
94        &self.psc
95    }
96    ///0x2c - auto-reload register
97    #[inline(always)]
98    pub const fn arr(&self) -> &ARR {
99        &self.arr
100    }
101    ///0x30 - repetition counter register
102    #[inline(always)]
103    pub const fn rcr(&self) -> &RCR {
104        &self.rcr
105    }
106    ///0x34..0x44 - capture/compare register
107    ///
108    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
109    #[inline(always)]
110    pub const fn ccr(&self, n: usize) -> &CCR {
111        &self.ccr[n]
112    }
113    ///Iterator for array of:
114    ///0x34..0x44 - capture/compare register
115    #[inline(always)]
116    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
117        self.ccr.iter()
118    }
119    ///0x34 - capture/compare register
120    #[inline(always)]
121    pub const fn ccr1(&self) -> &CCR {
122        self.ccr(0)
123    }
124    ///0x38 - capture/compare register
125    #[inline(always)]
126    pub const fn ccr2(&self) -> &CCR {
127        self.ccr(1)
128    }
129    ///0x3c - capture/compare register
130    #[inline(always)]
131    pub const fn ccr3(&self) -> &CCR {
132        self.ccr(2)
133    }
134    ///0x40 - capture/compare register
135    #[inline(always)]
136    pub const fn ccr4(&self) -> &CCR {
137        self.ccr(3)
138    }
139    ///0x44 - break and dead-time register
140    #[inline(always)]
141    pub const fn bdtr(&self) -> &BDTR {
142        &self.bdtr
143    }
144    ///0x48 - DMA control register
145    #[inline(always)]
146    pub const fn dcr(&self) -> &DCR {
147        &self.dcr
148    }
149    ///0x4c - DMA address for full transfer
150    #[inline(always)]
151    pub const fn dmar(&self) -> &DMAR {
152        &self.dmar
153    }
154    ///0x50 - option register 1
155    #[inline(always)]
156    pub const fn or1(&self) -> &OR1 {
157        &self.or1
158    }
159    ///0x54 - capture/compare mode register 2 (output mode)
160    #[inline(always)]
161    pub const fn ccmr3_output(&self) -> &CCMR3_OUTPUT {
162        &self.ccmr3_output
163    }
164    ///0x58 - capture/compare register
165    #[inline(always)]
166    pub const fn ccr5(&self) -> &CCR5 {
167        &self.ccr5
168    }
169    ///0x5c - capture/compare register
170    #[inline(always)]
171    pub const fn ccr6(&self) -> &CCR6 {
172        &self.ccr6
173    }
174    ///0x60 - DMA address for full transfer
175    #[inline(always)]
176    pub const fn af1(&self) -> &AF1 {
177        &self.af1
178    }
179    ///0x64 - DMA address for full transfer
180    #[inline(always)]
181    pub const fn af2(&self) -> &AF2 {
182        &self.af2
183    }
184    ///0x68 - TIM1 timer input selection register
185    #[inline(always)]
186    pub const fn tisel(&self) -> &TISEL {
187        &self.tisel
188    }
189}
190/**CR1 (rw) register accessor: control register 1
191
192You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
193
194See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CR1)
195
196For information about available fields see [`mod@cr1`]
197module*/
198pub type CR1 = crate::Reg<cr1::CR1rs>;
199///control register 1
200pub mod cr1;
201/**CR2 (rw) register accessor: control register 2
202
203You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
204
205See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CR2)
206
207For information about available fields see [`mod@cr2`]
208module*/
209pub type CR2 = crate::Reg<cr2::CR2rs>;
210///control register 2
211pub mod cr2;
212/**SMCR (rw) register accessor: slave mode control register
213
214You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
215
216See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:SMCR)
217
218For information about available fields see [`mod@smcr`]
219module*/
220pub type SMCR = crate::Reg<smcr::SMCRrs>;
221///slave mode control register
222pub mod smcr;
223/**DIER (rw) register accessor: DMA/Interrupt enable register
224
225You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
226
227See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:DIER)
228
229For information about available fields see [`mod@dier`]
230module*/
231pub type DIER = crate::Reg<dier::DIERrs>;
232///DMA/Interrupt enable register
233pub mod dier;
234/**SR (rw) register accessor: status register
235
236You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
237
238See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:SR)
239
240For information about available fields see [`mod@sr`]
241module*/
242pub type SR = crate::Reg<sr::SRrs>;
243///status register
244pub mod sr;
245/**EGR (w) register accessor: event generation register
246
247You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
248
249See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:EGR)
250
251For information about available fields see [`mod@egr`]
252module*/
253pub type EGR = crate::Reg<egr::EGRrs>;
254///event generation register
255pub mod egr;
256/**CCMR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)
257
258You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
259
260See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CCMR1_Output)
261
262For information about available fields see [`mod@ccmr1_output`]
263module*/
264#[doc(alias = "CCMR1_Output")]
265pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
266///capture/compare mode register 1 (output mode)
267pub mod ccmr1_output;
268/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (output mode)
269
270You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
271
272See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CCMR1_Input)
273
274For information about available fields see [`mod@ccmr1_input`]
275module*/
276#[doc(alias = "CCMR1_Input")]
277pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
278///capture/compare mode register 1 (output mode)
279pub mod ccmr1_input;
280/**CCMR2_Output (rw) register accessor: capture/compare mode register 2 (output mode)
281
282You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
283
284See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CCMR2_Output)
285
286For information about available fields see [`mod@ccmr2_output`]
287module*/
288#[doc(alias = "CCMR2_Output")]
289pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUTrs>;
290///capture/compare mode register 2 (output mode)
291pub mod ccmr2_output;
292/**CCMR2_Input (rw) register accessor: capture/compare mode register 2 (output mode)
293
294You can [`read`](crate::Reg::read) this register and get [`ccmr2_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
295
296See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CCMR2_Input)
297
298For information about available fields see [`mod@ccmr2_input`]
299module*/
300#[doc(alias = "CCMR2_Input")]
301pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUTrs>;
302///capture/compare mode register 2 (output mode)
303pub mod ccmr2_input;
304/**CCER (rw) register accessor: capture/compare enable register
305
306You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
307
308See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CCER)
309
310For information about available fields see [`mod@ccer`]
311module*/
312pub type CCER = crate::Reg<ccer::CCERrs>;
313///capture/compare enable register
314pub mod ccer;
315/**CNT (rw) register accessor: counter
316
317You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
318
319See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CNT)
320
321For information about available fields see [`mod@cnt`]
322module*/
323pub type CNT = crate::Reg<cnt::CNTrs>;
324///counter
325pub mod cnt;
326/**PSC (rw) register accessor: prescaler
327
328You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
329
330See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:PSC)
331
332For information about available fields see [`mod@psc`]
333module*/
334pub type PSC = crate::Reg<psc::PSCrs>;
335///prescaler
336pub mod psc;
337/**ARR (rw) register accessor: auto-reload register
338
339You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
340
341See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:ARR)
342
343For information about available fields see [`mod@arr`]
344module*/
345pub type ARR = crate::Reg<arr::ARRrs>;
346///auto-reload register
347pub mod arr;
348/**RCR (rw) register accessor: repetition counter register
349
350You can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
351
352See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:RCR)
353
354For information about available fields see [`mod@rcr`]
355module*/
356pub type RCR = crate::Reg<rcr::RCRrs>;
357///repetition counter register
358pub mod rcr;
359/**CCR (rw) register accessor: capture/compare register
360
361You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
362
363See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CCR[1])
364
365For information about available fields see [`mod@ccr`]
366module*/
367pub type CCR = crate::Reg<ccr::CCRrs>;
368///capture/compare register
369pub mod ccr;
370/**BDTR (rw) register accessor: break and dead-time register
371
372You can [`read`](crate::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
373
374See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:BDTR)
375
376For information about available fields see [`mod@bdtr`]
377module*/
378pub type BDTR = crate::Reg<bdtr::BDTRrs>;
379///break and dead-time register
380pub mod bdtr;
381/**DCR (rw) register accessor: DMA control register
382
383You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
384
385See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:DCR)
386
387For information about available fields see [`mod@dcr`]
388module*/
389pub type DCR = crate::Reg<dcr::DCRrs>;
390///DMA control register
391pub mod dcr;
392/**DMAR (rw) register accessor: DMA address for full transfer
393
394You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
395
396See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:DMAR)
397
398For information about available fields see [`mod@dmar`]
399module*/
400pub type DMAR = crate::Reg<dmar::DMARrs>;
401///DMA address for full transfer
402pub mod dmar;
403/**OR1 (rw) register accessor: option register 1
404
405You can [`read`](crate::Reg::read) this register and get [`or1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
406
407See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:OR1)
408
409For information about available fields see [`mod@or1`]
410module*/
411pub type OR1 = crate::Reg<or1::OR1rs>;
412///option register 1
413pub mod or1;
414/**CCMR3_Output (rw) register accessor: capture/compare mode register 2 (output mode)
415
416You can [`read`](crate::Reg::read) this register and get [`ccmr3_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr3_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
417
418See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CCMR3_Output)
419
420For information about available fields see [`mod@ccmr3_output`]
421module*/
422#[doc(alias = "CCMR3_Output")]
423pub type CCMR3_OUTPUT = crate::Reg<ccmr3_output::CCMR3_OUTPUTrs>;
424///capture/compare mode register 2 (output mode)
425pub mod ccmr3_output;
426/**CCR5 (rw) register accessor: capture/compare register
427
428You can [`read`](crate::Reg::read) this register and get [`ccr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
429
430See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:CCR5)
431
432For information about available fields see [`mod@ccr5`]
433module*/
434pub type CCR5 = crate::Reg<ccr5::CCR5rs>;
435///capture/compare register
436pub mod ccr5;
437pub use ccr as ccr6;
438pub use CCR as CCR6;
439/**AF1 (rw) register accessor: DMA address for full transfer
440
441You can [`read`](crate::Reg::read) this register and get [`af1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`af1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
442
443See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:AF1)
444
445For information about available fields see [`mod@af1`]
446module*/
447pub type AF1 = crate::Reg<af1::AF1rs>;
448///DMA address for full transfer
449pub mod af1;
450/**AF2 (rw) register accessor: DMA address for full transfer
451
452You can [`read`](crate::Reg::read) this register and get [`af2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`af2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
453
454See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:AF2)
455
456For information about available fields see [`mod@af2`]
457module*/
458pub type AF2 = crate::Reg<af2::AF2rs>;
459///DMA address for full transfer
460pub mod af2;
461/**TISEL (rw) register accessor: TIM1 timer input selection register
462
463You can [`read`](crate::Reg::read) this register and get [`tisel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
464
465See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM1:TISEL)
466
467For information about available fields see [`mod@tisel`]
468module*/
469pub type TISEL = crate::Reg<tisel::TISELrs>;
470///TIM1 timer input selection register
471pub mod tisel;
stm32g0_staging/stm32g0c1/tim1.rs

stm32g0_staging/stm32g0c1/
tim1.rs
