stm32g0_staging/stm32g0c1/rng/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5///Field `RNGEN` reader - True random number generator enable
6pub type RNGEN_R = crate::BitReader;
7///Field `RNGEN` writer - True random number generator enable
8pub type RNGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9///Field `IE` reader - Interrupt Enable
10pub type IE_R = crate::BitReader;
11///Field `IE` writer - Interrupt Enable
12pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `CED` reader - Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled.
14pub type CED_R = crate::BitReader;
15///Field `CED` writer - Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled.
16pub type CED_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    ///Bit 2 - True random number generator enable
19    #[inline(always)]
20    pub fn rngen(&self) -> RNGEN_R {
21        RNGEN_R::new(((self.bits >> 2) & 1) != 0)
22    }
23    ///Bit 3 - Interrupt Enable
24    #[inline(always)]
25    pub fn ie(&self) -> IE_R {
26        IE_R::new(((self.bits >> 3) & 1) != 0)
27    }
28    ///Bit 5 - Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled.
29    #[inline(always)]
30    pub fn ced(&self) -> CED_R {
31        CED_R::new(((self.bits >> 5) & 1) != 0)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("CR")
37            .field("rngen", &self.rngen())
38            .field("ie", &self.ie())
39            .field("ced", &self.ced())
40            .finish()
41    }
42}
43impl W {
44    ///Bit 2 - True random number generator enable
45    #[inline(always)]
46    pub fn rngen(&mut self) -> RNGEN_W<CRrs> {
47        RNGEN_W::new(self, 2)
48    }
49    ///Bit 3 - Interrupt Enable
50    #[inline(always)]
51    pub fn ie(&mut self) -> IE_W<CRrs> {
52        IE_W::new(self, 3)
53    }
54    ///Bit 5 - Clock error detection The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled, i.e. to enable or disable CED the RNG must be disabled.
55    #[inline(always)]
56    pub fn ced(&mut self) -> CED_W<CRrs> {
57        CED_W::new(self, 5)
58    }
59}
60/**control register
61
62You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63
64See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RNG:CR)*/
65pub struct CRrs;
66impl crate::RegisterSpec for CRrs {
67    type Ux = u32;
68}
69///`read()` method returns [`cr::R`](R) reader structure
70impl crate::Readable for CRrs {}
71///`write(|w| ..)` method takes [`cr::W`](W) writer structure
72impl crate::Writable for CRrs {
73    type Safety = crate::Unsafe;
74    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
75    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
76}
77///`reset()` method sets CR to value 0
78impl crate::Resettable for CRrs {
79    const RESET_VALUE: u32 = 0;
80}
stm32g0_staging/stm32g0c1/rng/cr.rs

stm32g0_staging/stm32g0c1/rng/
cr.rs
