stm32g0_staging/stm32g0c1/
rcc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    icscr: ICSCR,
7    cfgr: CFGR,
8    pllcfgr: PLLCFGR,
9    _reserved4: [u8; 0x04],
10    crrcr: CRRCR,
11    cier: CIER,
12    cifr: CIFR,
13    cicr: CICR,
14    ioprstr: IOPRSTR,
15    ahbrstr: AHBRSTR,
16    apbrstr1: APBRSTR1,
17    apbrstr2: APBRSTR2,
18    iopenr: IOPENR,
19    ahbenr: AHBENR,
20    apbenr1: APBENR1,
21    apbenr2: APBENR2,
22    iopsmenr: IOPSMENR,
23    ahbsmenr: AHBSMENR,
24    apbsmenr1: APBSMENR1,
25    apbsmenr2: APBSMENR2,
26    ccipr: CCIPR,
27    ccipr2: CCIPR2,
28    bdcr: BDCR,
29    csr: CSR,
30}
31impl RegisterBlock {
32    ///0x00 - Clock control register
33    #[inline(always)]
34    pub const fn cr(&self) -> &CR {
35        &self.cr
36    }
37    ///0x04 - Internal clock sources calibration register
38    #[inline(always)]
39    pub const fn icscr(&self) -> &ICSCR {
40        &self.icscr
41    }
42    ///0x08 - Clock configuration register
43    #[inline(always)]
44    pub const fn cfgr(&self) -> &CFGR {
45        &self.cfgr
46    }
47    ///0x0c - PLL configuration register
48    #[inline(always)]
49    pub const fn pllcfgr(&self) -> &PLLCFGR {
50        &self.pllcfgr
51    }
52    ///0x14 - RCC clock recovery RC register
53    #[inline(always)]
54    pub const fn crrcr(&self) -> &CRRCR {
55        &self.crrcr
56    }
57    ///0x18 - Clock interrupt enable register
58    #[inline(always)]
59    pub const fn cier(&self) -> &CIER {
60        &self.cier
61    }
62    ///0x1c - Clock interrupt flag register
63    #[inline(always)]
64    pub const fn cifr(&self) -> &CIFR {
65        &self.cifr
66    }
67    ///0x20 - Clock interrupt clear register
68    #[inline(always)]
69    pub const fn cicr(&self) -> &CICR {
70        &self.cicr
71    }
72    ///0x24 - I/O port reset register
73    #[inline(always)]
74    pub const fn ioprstr(&self) -> &IOPRSTR {
75        &self.ioprstr
76    }
77    ///0x28 - AHB peripheral reset register
78    #[inline(always)]
79    pub const fn ahbrstr(&self) -> &AHBRSTR {
80        &self.ahbrstr
81    }
82    ///0x2c - APB peripheral reset register 1
83    #[inline(always)]
84    pub const fn apbrstr1(&self) -> &APBRSTR1 {
85        &self.apbrstr1
86    }
87    ///0x30 - APB peripheral reset register 2
88    #[inline(always)]
89    pub const fn apbrstr2(&self) -> &APBRSTR2 {
90        &self.apbrstr2
91    }
92    ///0x34 - GPIO clock enable register
93    #[inline(always)]
94    pub const fn iopenr(&self) -> &IOPENR {
95        &self.iopenr
96    }
97    ///0x38 - AHB peripheral clock enable register
98    #[inline(always)]
99    pub const fn ahbenr(&self) -> &AHBENR {
100        &self.ahbenr
101    }
102    ///0x3c - APB peripheral clock enable register 1
103    #[inline(always)]
104    pub const fn apbenr1(&self) -> &APBENR1 {
105        &self.apbenr1
106    }
107    ///0x40 - APB peripheral clock enable register 2
108    #[inline(always)]
109    pub const fn apbenr2(&self) -> &APBENR2 {
110        &self.apbenr2
111    }
112    ///0x44 - GPIO in Sleep mode clock enable register
113    #[inline(always)]
114    pub const fn iopsmenr(&self) -> &IOPSMENR {
115        &self.iopsmenr
116    }
117    ///0x48 - AHB peripheral clock enable in Sleep mode register
118    #[inline(always)]
119    pub const fn ahbsmenr(&self) -> &AHBSMENR {
120        &self.ahbsmenr
121    }
122    ///0x4c - APB peripheral clock enable in Sleep mode register 1
123    #[inline(always)]
124    pub const fn apbsmenr1(&self) -> &APBSMENR1 {
125        &self.apbsmenr1
126    }
127    ///0x50 - APB peripheral clock enable in Sleep mode register 2
128    #[inline(always)]
129    pub const fn apbsmenr2(&self) -> &APBSMENR2 {
130        &self.apbsmenr2
131    }
132    ///0x54 - Peripherals independent clock configuration register
133    #[inline(always)]
134    pub const fn ccipr(&self) -> &CCIPR {
135        &self.ccipr
136    }
137    ///0x58 - Peripherals independent clock configuration register 2
138    #[inline(always)]
139    pub const fn ccipr2(&self) -> &CCIPR2 {
140        &self.ccipr2
141    }
142    ///0x5c - RTC domain control register
143    #[inline(always)]
144    pub const fn bdcr(&self) -> &BDCR {
145        &self.bdcr
146    }
147    ///0x60 - Control/status register
148    #[inline(always)]
149    pub const fn csr(&self) -> &CSR {
150        &self.csr
151    }
152}
153/**CR (rw) register accessor: Clock control register
154
155You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
156
157See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:CR)
158
159For information about available fields see [`mod@cr`]
160module*/
161pub type CR = crate::Reg<cr::CRrs>;
162///Clock control register
163pub mod cr;
164/**ICSCR (rw) register accessor: Internal clock sources calibration register
165
166You can [`read`](crate::Reg::read) this register and get [`icscr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icscr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:ICSCR)
169
170For information about available fields see [`mod@icscr`]
171module*/
172pub type ICSCR = crate::Reg<icscr::ICSCRrs>;
173///Internal clock sources calibration register
174pub mod icscr;
175/**CFGR (rw) register accessor: Clock configuration register
176
177You can [`read`](crate::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
178
179See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:CFGR)
180
181For information about available fields see [`mod@cfgr`]
182module*/
183pub type CFGR = crate::Reg<cfgr::CFGRrs>;
184///Clock configuration register
185pub mod cfgr;
186/**PLLCFGR (rw) register accessor: PLL configuration register
187
188You can [`read`](crate::Reg::read) this register and get [`pllcfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
189
190See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:PLLCFGR)
191
192For information about available fields see [`mod@pllcfgr`]
193module*/
194pub type PLLCFGR = crate::Reg<pllcfgr::PLLCFGRrs>;
195///PLL configuration register
196pub mod pllcfgr;
197/**CRRCR (r) register accessor: RCC clock recovery RC register
198
199You can [`read`](crate::Reg::read) this register and get [`crrcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
200
201See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:CRRCR)
202
203For information about available fields see [`mod@crrcr`]
204module*/
205pub type CRRCR = crate::Reg<crrcr::CRRCRrs>;
206///RCC clock recovery RC register
207pub mod crrcr;
208/**CIER (rw) register accessor: Clock interrupt enable register
209
210You can [`read`](crate::Reg::read) this register and get [`cier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
211
212See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:CIER)
213
214For information about available fields see [`mod@cier`]
215module*/
216pub type CIER = crate::Reg<cier::CIERrs>;
217///Clock interrupt enable register
218pub mod cier;
219/**CIFR (r) register accessor: Clock interrupt flag register
220
221You can [`read`](crate::Reg::read) this register and get [`cifr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
222
223See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:CIFR)
224
225For information about available fields see [`mod@cifr`]
226module*/
227pub type CIFR = crate::Reg<cifr::CIFRrs>;
228///Clock interrupt flag register
229pub mod cifr;
230/**CICR (w) register accessor: Clock interrupt clear register
231
232You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cicr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
233
234See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:CICR)
235
236For information about available fields see [`mod@cicr`]
237module*/
238pub type CICR = crate::Reg<cicr::CICRrs>;
239///Clock interrupt clear register
240pub mod cicr;
241/**IOPRSTR (rw) register accessor: I/O port reset register
242
243You can [`read`](crate::Reg::read) this register and get [`ioprstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioprstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
244
245See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:IOPRSTR)
246
247For information about available fields see [`mod@ioprstr`]
248module*/
249pub type IOPRSTR = crate::Reg<ioprstr::IOPRSTRrs>;
250///I/O port reset register
251pub mod ioprstr;
252/**AHBRSTR (rw) register accessor: AHB peripheral reset register
253
254You can [`read`](crate::Reg::read) this register and get [`ahbrstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbrstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
255
256See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:AHBRSTR)
257
258For information about available fields see [`mod@ahbrstr`]
259module*/
260pub type AHBRSTR = crate::Reg<ahbrstr::AHBRSTRrs>;
261///AHB peripheral reset register
262pub mod ahbrstr;
263/**APBRSTR1 (rw) register accessor: APB peripheral reset register 1
264
265You can [`read`](crate::Reg::read) this register and get [`apbrstr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbrstr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
266
267See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:APBRSTR1)
268
269For information about available fields see [`mod@apbrstr1`]
270module*/
271pub type APBRSTR1 = crate::Reg<apbrstr1::APBRSTR1rs>;
272///APB peripheral reset register 1
273pub mod apbrstr1;
274/**APBRSTR2 (rw) register accessor: APB peripheral reset register 2
275
276You can [`read`](crate::Reg::read) this register and get [`apbrstr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbrstr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
277
278See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:APBRSTR2)
279
280For information about available fields see [`mod@apbrstr2`]
281module*/
282pub type APBRSTR2 = crate::Reg<apbrstr2::APBRSTR2rs>;
283///APB peripheral reset register 2
284pub mod apbrstr2;
285/**IOPENR (rw) register accessor: GPIO clock enable register
286
287You can [`read`](crate::Reg::read) this register and get [`iopenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iopenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
288
289See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:IOPENR)
290
291For information about available fields see [`mod@iopenr`]
292module*/
293pub type IOPENR = crate::Reg<iopenr::IOPENRrs>;
294///GPIO clock enable register
295pub mod iopenr;
296/**AHBENR (rw) register accessor: AHB peripheral clock enable register
297
298You can [`read`](crate::Reg::read) this register and get [`ahbenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
299
300See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:AHBENR)
301
302For information about available fields see [`mod@ahbenr`]
303module*/
304pub type AHBENR = crate::Reg<ahbenr::AHBENRrs>;
305///AHB peripheral clock enable register
306pub mod ahbenr;
307/**APBENR1 (rw) register accessor: APB peripheral clock enable register 1
308
309You can [`read`](crate::Reg::read) this register and get [`apbenr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbenr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
310
311See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:APBENR1)
312
313For information about available fields see [`mod@apbenr1`]
314module*/
315pub type APBENR1 = crate::Reg<apbenr1::APBENR1rs>;
316///APB peripheral clock enable register 1
317pub mod apbenr1;
318/**APBENR2 (rw) register accessor: APB peripheral clock enable register 2
319
320You can [`read`](crate::Reg::read) this register and get [`apbenr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbenr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
321
322See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:APBENR2)
323
324For information about available fields see [`mod@apbenr2`]
325module*/
326pub type APBENR2 = crate::Reg<apbenr2::APBENR2rs>;
327///APB peripheral clock enable register 2
328pub mod apbenr2;
329/**IOPSMENR (rw) register accessor: GPIO in Sleep mode clock enable register
330
331You can [`read`](crate::Reg::read) this register and get [`iopsmenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iopsmenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
332
333See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:IOPSMENR)
334
335For information about available fields see [`mod@iopsmenr`]
336module*/
337pub type IOPSMENR = crate::Reg<iopsmenr::IOPSMENRrs>;
338///GPIO in Sleep mode clock enable register
339pub mod iopsmenr;
340/**AHBSMENR (rw) register accessor: AHB peripheral clock enable in Sleep mode register
341
342You can [`read`](crate::Reg::read) this register and get [`ahbsmenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbsmenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
343
344See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:AHBSMENR)
345
346For information about available fields see [`mod@ahbsmenr`]
347module*/
348pub type AHBSMENR = crate::Reg<ahbsmenr::AHBSMENRrs>;
349///AHB peripheral clock enable in Sleep mode register
350pub mod ahbsmenr;
351/**APBSMENR1 (rw) register accessor: APB peripheral clock enable in Sleep mode register 1
352
353You can [`read`](crate::Reg::read) this register and get [`apbsmenr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbsmenr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
354
355See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:APBSMENR1)
356
357For information about available fields see [`mod@apbsmenr1`]
358module*/
359pub type APBSMENR1 = crate::Reg<apbsmenr1::APBSMENR1rs>;
360///APB peripheral clock enable in Sleep mode register 1
361pub mod apbsmenr1;
362/**APBSMENR2 (rw) register accessor: APB peripheral clock enable in Sleep mode register 2
363
364You can [`read`](crate::Reg::read) this register and get [`apbsmenr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbsmenr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
365
366See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:APBSMENR2)
367
368For information about available fields see [`mod@apbsmenr2`]
369module*/
370pub type APBSMENR2 = crate::Reg<apbsmenr2::APBSMENR2rs>;
371///APB peripheral clock enable in Sleep mode register 2
372pub mod apbsmenr2;
373/**CCIPR (rw) register accessor: Peripherals independent clock configuration register
374
375You can [`read`](crate::Reg::read) this register and get [`ccipr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccipr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
376
377See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:CCIPR)
378
379For information about available fields see [`mod@ccipr`]
380module*/
381pub type CCIPR = crate::Reg<ccipr::CCIPRrs>;
382///Peripherals independent clock configuration register
383pub mod ccipr;
384/**CCIPR2 (rw) register accessor: Peripherals independent clock configuration register 2
385
386You can [`read`](crate::Reg::read) this register and get [`ccipr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccipr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
387
388See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:CCIPR2)
389
390For information about available fields see [`mod@ccipr2`]
391module*/
392pub type CCIPR2 = crate::Reg<ccipr2::CCIPR2rs>;
393///Peripherals independent clock configuration register 2
394pub mod ccipr2;
395/**BDCR (rw) register accessor: RTC domain control register
396
397You can [`read`](crate::Reg::read) this register and get [`bdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
398
399See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:BDCR)
400
401For information about available fields see [`mod@bdcr`]
402module*/
403pub type BDCR = crate::Reg<bdcr::BDCRrs>;
404///RTC domain control register
405pub mod bdcr;
406/**CSR (rw) register accessor: Control/status register
407
408You can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
409
410See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#RCC:CSR)
411
412For information about available fields see [`mod@csr`]
413module*/
414pub type CSR = crate::Reg<csr::CSRrs>;
415///Control/status register
416pub mod csr;
stm32g0_staging/stm32g0c1/rcc.rs

stm32g0_staging/stm32g0c1/
rcc.rs
