stm32g0_staging/stm32g0c1/
dbg.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    idcode: IDCODE,
6    cr: CR,
7    apb_fz1: APB_FZ1,
8    apb_fz2: APB_FZ2,
9}
10impl RegisterBlock {
11    ///0x00 - MCU Device ID Code Register
12    #[inline(always)]
13    pub const fn idcode(&self) -> &IDCODE {
14        &self.idcode
15    }
16    ///0x04 - DBG configuration register
17    #[inline(always)]
18    pub const fn cr(&self) -> &CR {
19        &self.cr
20    }
21    ///0x08 - DBG APB freeze register 1
22    #[inline(always)]
23    pub const fn apb_fz1(&self) -> &APB_FZ1 {
24        &self.apb_fz1
25    }
26    ///0x0c - DBG APB freeze register 2
27    #[inline(always)]
28    pub const fn apb_fz2(&self) -> &APB_FZ2 {
29        &self.apb_fz2
30    }
31}
32/**IDCODE (r) register accessor: MCU Device ID Code Register
33
34You can [`read`](crate::Reg::read) this register and get [`idcode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
35
36See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DBG:IDCODE)
37
38For information about available fields see [`mod@idcode`]
39module*/
40pub type IDCODE = crate::Reg<idcode::IDCODErs>;
41///MCU Device ID Code Register
42pub mod idcode;
43/**CR (rw) register accessor: DBG configuration register
44
45You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
46
47See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DBG:CR)
48
49For information about available fields see [`mod@cr`]
50module*/
51pub type CR = crate::Reg<cr::CRrs>;
52///DBG configuration register
53pub mod cr;
54/**APB_FZ1 (rw) register accessor: DBG APB freeze register 1
55
56You can [`read`](crate::Reg::read) this register and get [`apb_fz1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_fz1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
57
58See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DBG:APB_FZ1)
59
60For information about available fields see [`mod@apb_fz1`]
61module*/
62pub type APB_FZ1 = crate::Reg<apb_fz1::APB_FZ1rs>;
63///DBG APB freeze register 1
64pub mod apb_fz1;
65/**APB_FZ2 (rw) register accessor: DBG APB freeze register 2
66
67You can [`read`](crate::Reg::read) this register and get [`apb_fz2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_fz2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
68
69See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DBG:APB_FZ2)
70
71For information about available fields see [`mod@apb_fz2`]
72module*/
73pub type APB_FZ2 = crate::Reg<apb_fz2::APB_FZ2rs>;
74///DBG APB freeze register 2
75pub mod apb_fz2;
stm32g0_staging/stm32g0c1/dbg.rs

stm32g0_staging/stm32g0c1/
dbg.rs
