stm32g0_staging/stm32g0c1/
dac.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    swtrgr: SWTRGR,
7    dhr12r1: DHR12R1,
8    dhr12l1: DHR12L1,
9    dhr8r1: DHR8R1,
10    dhr12r2: DHR12R2,
11    dhr12l2: DHR12L2,
12    dhr8r2: DHR8R2,
13    dhr12rd: DHR12RD,
14    dhr12ld: DHR12LD,
15    dhr8rd: DHR8RD,
16    dor1: DOR1,
17    dor2: DOR2,
18    sr: SR,
19    ccr: CCR,
20    mcr: MCR,
21    shsr1: SHSR1,
22    shsr2: SHSR2,
23    shhr: SHHR,
24    shrr: SHRR,
25}
26impl RegisterBlock {
27    ///0x00 - DAC control register
28    #[inline(always)]
29    pub const fn cr(&self) -> &CR {
30        &self.cr
31    }
32    ///0x04 - DAC software trigger register
33    #[inline(always)]
34    pub const fn swtrgr(&self) -> &SWTRGR {
35        &self.swtrgr
36    }
37    ///0x08 - DAC channel1 12-bit right-aligned data holding register
38    #[inline(always)]
39    pub const fn dhr12r1(&self) -> &DHR12R1 {
40        &self.dhr12r1
41    }
42    ///0x0c - DAC channel1 12-bit left aligned data holding register
43    #[inline(always)]
44    pub const fn dhr12l1(&self) -> &DHR12L1 {
45        &self.dhr12l1
46    }
47    ///0x10 - DAC channel1 8-bit right aligned data holding register
48    #[inline(always)]
49    pub const fn dhr8r1(&self) -> &DHR8R1 {
50        &self.dhr8r1
51    }
52    ///0x14 - DAC channel2 12-bit right aligned data holding register
53    #[inline(always)]
54    pub const fn dhr12r2(&self) -> &DHR12R2 {
55        &self.dhr12r2
56    }
57    ///0x18 - DAC channel2 12-bit left aligned data holding register
58    #[inline(always)]
59    pub const fn dhr12l2(&self) -> &DHR12L2 {
60        &self.dhr12l2
61    }
62    ///0x1c - DAC channel2 8-bit right-aligned data holding register
63    #[inline(always)]
64    pub const fn dhr8r2(&self) -> &DHR8R2 {
65        &self.dhr8r2
66    }
67    ///0x20 - Dual DAC 12-bit right-aligned data holding register
68    #[inline(always)]
69    pub const fn dhr12rd(&self) -> &DHR12RD {
70        &self.dhr12rd
71    }
72    ///0x24 - DUAL DAC 12-bit left aligned data holding register
73    #[inline(always)]
74    pub const fn dhr12ld(&self) -> &DHR12LD {
75        &self.dhr12ld
76    }
77    ///0x28 - DUAL DAC 8-bit right aligned data holding register
78    #[inline(always)]
79    pub const fn dhr8rd(&self) -> &DHR8RD {
80        &self.dhr8rd
81    }
82    ///0x2c - DAC channel1 data output register
83    #[inline(always)]
84    pub const fn dor1(&self) -> &DOR1 {
85        &self.dor1
86    }
87    ///0x30 - DAC channel2 data output register
88    #[inline(always)]
89    pub const fn dor2(&self) -> &DOR2 {
90        &self.dor2
91    }
92    ///0x34 - DAC status register
93    #[inline(always)]
94    pub const fn sr(&self) -> &SR {
95        &self.sr
96    }
97    ///0x38 - DAC calibration control register
98    #[inline(always)]
99    pub const fn ccr(&self) -> &CCR {
100        &self.ccr
101    }
102    ///0x3c - DAC mode control register
103    #[inline(always)]
104    pub const fn mcr(&self) -> &MCR {
105        &self.mcr
106    }
107    ///0x40 - DAC Sample and Hold sample time register 1
108    #[inline(always)]
109    pub const fn shsr1(&self) -> &SHSR1 {
110        &self.shsr1
111    }
112    ///0x44 - DAC Sample and Hold sample time register 2
113    #[inline(always)]
114    pub const fn shsr2(&self) -> &SHSR2 {
115        &self.shsr2
116    }
117    ///0x48 - DAC Sample and Hold hold time register
118    #[inline(always)]
119    pub const fn shhr(&self) -> &SHHR {
120        &self.shhr
121    }
122    ///0x4c - DAC Sample and Hold refresh time register
123    #[inline(always)]
124    pub const fn shrr(&self) -> &SHRR {
125        &self.shrr
126    }
127}
128/**CR (rw) register accessor: DAC control register
129
130You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
131
132See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:CR)
133
134For information about available fields see [`mod@cr`]
135module*/
136pub type CR = crate::Reg<cr::CRrs>;
137///DAC control register
138pub mod cr;
139/**SWTRGR (w) register accessor: DAC software trigger register
140
141You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swtrgr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
142
143See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:SWTRGR)
144
145For information about available fields see [`mod@swtrgr`]
146module*/
147pub type SWTRGR = crate::Reg<swtrgr::SWTRGRrs>;
148///DAC software trigger register
149pub mod swtrgr;
150/**DHR12R1 (rw) register accessor: DAC channel1 12-bit right-aligned data holding register
151
152You can [`read`](crate::Reg::read) this register and get [`dhr12r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
153
154See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DHR12R1)
155
156For information about available fields see [`mod@dhr12r1`]
157module*/
158pub type DHR12R1 = crate::Reg<dhr12r1::DHR12R1rs>;
159///DAC channel1 12-bit right-aligned data holding register
160pub mod dhr12r1;
161/**DHR12L1 (rw) register accessor: DAC channel1 12-bit left aligned data holding register
162
163You can [`read`](crate::Reg::read) this register and get [`dhr12l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
164
165See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DHR12L1)
166
167For information about available fields see [`mod@dhr12l1`]
168module*/
169pub type DHR12L1 = crate::Reg<dhr12l1::DHR12L1rs>;
170///DAC channel1 12-bit left aligned data holding register
171pub mod dhr12l1;
172/**DHR8R1 (rw) register accessor: DAC channel1 8-bit right aligned data holding register
173
174You can [`read`](crate::Reg::read) this register and get [`dhr8r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
175
176See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DHR8R1)
177
178For information about available fields see [`mod@dhr8r1`]
179module*/
180pub type DHR8R1 = crate::Reg<dhr8r1::DHR8R1rs>;
181///DAC channel1 8-bit right aligned data holding register
182pub mod dhr8r1;
183/**DHR12R2 (rw) register accessor: DAC channel2 12-bit right aligned data holding register
184
185You can [`read`](crate::Reg::read) this register and get [`dhr12r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
186
187See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DHR12R2)
188
189For information about available fields see [`mod@dhr12r2`]
190module*/
191pub type DHR12R2 = crate::Reg<dhr12r2::DHR12R2rs>;
192///DAC channel2 12-bit right aligned data holding register
193pub mod dhr12r2;
194/**DHR12L2 (rw) register accessor: DAC channel2 12-bit left aligned data holding register
195
196You can [`read`](crate::Reg::read) this register and get [`dhr12l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
197
198See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DHR12L2)
199
200For information about available fields see [`mod@dhr12l2`]
201module*/
202pub type DHR12L2 = crate::Reg<dhr12l2::DHR12L2rs>;
203///DAC channel2 12-bit left aligned data holding register
204pub mod dhr12l2;
205/**DHR8R2 (rw) register accessor: DAC channel2 8-bit right-aligned data holding register
206
207You can [`read`](crate::Reg::read) this register and get [`dhr8r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
208
209See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DHR8R2)
210
211For information about available fields see [`mod@dhr8r2`]
212module*/
213pub type DHR8R2 = crate::Reg<dhr8r2::DHR8R2rs>;
214///DAC channel2 8-bit right-aligned data holding register
215pub mod dhr8r2;
216/**DHR12RD (rw) register accessor: Dual DAC 12-bit right-aligned data holding register
217
218You can [`read`](crate::Reg::read) this register and get [`dhr12rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
219
220See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DHR12RD)
221
222For information about available fields see [`mod@dhr12rd`]
223module*/
224pub type DHR12RD = crate::Reg<dhr12rd::DHR12RDrs>;
225///Dual DAC 12-bit right-aligned data holding register
226pub mod dhr12rd;
227/**DHR12LD (rw) register accessor: DUAL DAC 12-bit left aligned data holding register
228
229You can [`read`](crate::Reg::read) this register and get [`dhr12ld::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr12ld::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
230
231See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DHR12LD)
232
233For information about available fields see [`mod@dhr12ld`]
234module*/
235pub type DHR12LD = crate::Reg<dhr12ld::DHR12LDrs>;
236///DUAL DAC 12-bit left aligned data holding register
237pub mod dhr12ld;
238/**DHR8RD (rw) register accessor: DUAL DAC 8-bit right aligned data holding register
239
240You can [`read`](crate::Reg::read) this register and get [`dhr8rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhr8rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
241
242See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DHR8RD)
243
244For information about available fields see [`mod@dhr8rd`]
245module*/
246pub type DHR8RD = crate::Reg<dhr8rd::DHR8RDrs>;
247///DUAL DAC 8-bit right aligned data holding register
248pub mod dhr8rd;
249/**DOR1 (r) register accessor: DAC channel1 data output register
250
251You can [`read`](crate::Reg::read) this register and get [`dor1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
252
253See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DOR1)
254
255For information about available fields see [`mod@dor1`]
256module*/
257pub type DOR1 = crate::Reg<dor1::DOR1rs>;
258///DAC channel1 data output register
259pub mod dor1;
260/**DOR2 (r) register accessor: DAC channel2 data output register
261
262You can [`read`](crate::Reg::read) this register and get [`dor2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
263
264See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:DOR2)
265
266For information about available fields see [`mod@dor2`]
267module*/
268pub type DOR2 = crate::Reg<dor2::DOR2rs>;
269///DAC channel2 data output register
270pub mod dor2;
271/**SR (rw) register accessor: DAC status register
272
273You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
274
275See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:SR)
276
277For information about available fields see [`mod@sr`]
278module*/
279pub type SR = crate::Reg<sr::SRrs>;
280///DAC status register
281pub mod sr;
282/**CCR (rw) register accessor: DAC calibration control register
283
284You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
285
286See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:CCR)
287
288For information about available fields see [`mod@ccr`]
289module*/
290pub type CCR = crate::Reg<ccr::CCRrs>;
291///DAC calibration control register
292pub mod ccr;
293/**MCR (rw) register accessor: DAC mode control register
294
295You can [`read`](crate::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
296
297See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:MCR)
298
299For information about available fields see [`mod@mcr`]
300module*/
301pub type MCR = crate::Reg<mcr::MCRrs>;
302///DAC mode control register
303pub mod mcr;
304/**SHSR1 (rw) register accessor: DAC Sample and Hold sample time register 1
305
306You can [`read`](crate::Reg::read) this register and get [`shsr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shsr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
307
308See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:SHSR1)
309
310For information about available fields see [`mod@shsr1`]
311module*/
312pub type SHSR1 = crate::Reg<shsr1::SHSR1rs>;
313///DAC Sample and Hold sample time register 1
314pub mod shsr1;
315/**SHSR2 (rw) register accessor: DAC Sample and Hold sample time register 2
316
317You can [`read`](crate::Reg::read) this register and get [`shsr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shsr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
318
319See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:SHSR2)
320
321For information about available fields see [`mod@shsr2`]
322module*/
323pub type SHSR2 = crate::Reg<shsr2::SHSR2rs>;
324///DAC Sample and Hold sample time register 2
325pub mod shsr2;
326/**SHHR (rw) register accessor: DAC Sample and Hold hold time register
327
328You can [`read`](crate::Reg::read) this register and get [`shhr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shhr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
329
330See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:SHHR)
331
332For information about available fields see [`mod@shhr`]
333module*/
334pub type SHHR = crate::Reg<shhr::SHHRrs>;
335///DAC Sample and Hold hold time register
336pub mod shhr;
337/**SHRR (rw) register accessor: DAC Sample and Hold refresh time register
338
339You can [`read`](crate::Reg::read) this register and get [`shrr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shrr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
340
341See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#DAC:SHRR)
342
343For information about available fields see [`mod@shrr`]
344module*/
345pub type SHRR = crate::Reg<shrr::SHRRrs>;
346///DAC Sample and Hold refresh time register
347pub mod shrr;
stm32g0_staging/stm32g0c1/dac.rs

stm32g0_staging/stm32g0c1/
dac.rs
