stm32g0_staging/stm32g0b0/
usb.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    chepr: [CHEPR; 8],
6    _reserved1: [u8; 0x20],
7    cntr: CNTR,
8    istr: ISTR,
9    fnr: FNR,
10    daddr: DADDR,
11    _reserved5: [u8; 0x04],
12    lpmcsr: LPMCSR,
13    bcdr: BCDR,
14}
15impl RegisterBlock {
16    ///0x00..0x20 - USB endpoint/channel %s register
17    #[inline(always)]
18    pub const fn chepr(&self, n: usize) -> &CHEPR {
19        &self.chepr[n]
20    }
21    ///Iterator for array of:
22    ///0x00..0x20 - USB endpoint/channel %s register
23    #[inline(always)]
24    pub fn chepr_iter(&self) -> impl Iterator<Item = &CHEPR> {
25        self.chepr.iter()
26    }
27    ///0x00 - USB endpoint/channel 0 register
28    #[inline(always)]
29    pub const fn chep0r(&self) -> &CHEPR {
30        self.chepr(0)
31    }
32    ///0x04 - USB endpoint/channel 1 register
33    #[inline(always)]
34    pub const fn chep1r(&self) -> &CHEPR {
35        self.chepr(1)
36    }
37    ///0x08 - USB endpoint/channel 2 register
38    #[inline(always)]
39    pub const fn chep2r(&self) -> &CHEPR {
40        self.chepr(2)
41    }
42    ///0x0c - USB endpoint/channel 3 register
43    #[inline(always)]
44    pub const fn chep3r(&self) -> &CHEPR {
45        self.chepr(3)
46    }
47    ///0x10 - USB endpoint/channel 4 register
48    #[inline(always)]
49    pub const fn chep4r(&self) -> &CHEPR {
50        self.chepr(4)
51    }
52    ///0x14 - USB endpoint/channel 5 register
53    #[inline(always)]
54    pub const fn chep5r(&self) -> &CHEPR {
55        self.chepr(5)
56    }
57    ///0x18 - USB endpoint/channel 6 register
58    #[inline(always)]
59    pub const fn chep6r(&self) -> &CHEPR {
60        self.chepr(6)
61    }
62    ///0x1c - USB endpoint/channel 7 register
63    #[inline(always)]
64    pub const fn chep7r(&self) -> &CHEPR {
65        self.chepr(7)
66    }
67    ///0x40 -
68    #[inline(always)]
69    pub const fn cntr(&self) -> &CNTR {
70        &self.cntr
71    }
72    ///0x44 - USB interrupt status register
73    #[inline(always)]
74    pub const fn istr(&self) -> &ISTR {
75        &self.istr
76    }
77    ///0x48 - USB frame number register
78    #[inline(always)]
79    pub const fn fnr(&self) -> &FNR {
80        &self.fnr
81    }
82    ///0x4c -
83    #[inline(always)]
84    pub const fn daddr(&self) -> &DADDR {
85        &self.daddr
86    }
87    ///0x54 -
88    #[inline(always)]
89    pub const fn lpmcsr(&self) -> &LPMCSR {
90        &self.lpmcsr
91    }
92    ///0x58 -
93    #[inline(always)]
94    pub const fn bcdr(&self) -> &BCDR {
95        &self.bcdr
96    }
97}
98/**CHEPR (rw) register accessor: USB endpoint/channel %s register
99
100You can [`read`](crate::Reg::read) this register and get [`chepr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chepr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
101
102See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#USB:CHEP[0]R)
103
104For information about available fields see [`mod@chepr`]
105module*/
106pub type CHEPR = crate::Reg<chepr::CHEPRrs>;
107///USB endpoint/channel %s register
108pub mod chepr;
109/**CNTR (rw) register accessor:
110
111You can [`read`](crate::Reg::read) this register and get [`cntr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cntr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
112
113See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#USB:CNTR)
114
115For information about available fields see [`mod@cntr`]
116module*/
117pub type CNTR = crate::Reg<cntr::CNTRrs>;
118///
119pub mod cntr;
120/**ISTR (rw) register accessor: USB interrupt status register
121
122You can [`read`](crate::Reg::read) this register and get [`istr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`istr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#USB:ISTR)
125
126For information about available fields see [`mod@istr`]
127module*/
128pub type ISTR = crate::Reg<istr::ISTRrs>;
129///USB interrupt status register
130pub mod istr;
131/**FNR (r) register accessor: USB frame number register
132
133You can [`read`](crate::Reg::read) this register and get [`fnr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
134
135See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#USB:FNR)
136
137For information about available fields see [`mod@fnr`]
138module*/
139pub type FNR = crate::Reg<fnr::FNRrs>;
140///USB frame number register
141pub mod fnr;
142/**DADDR (rw) register accessor:
143
144You can [`read`](crate::Reg::read) this register and get [`daddr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`daddr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
145
146See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#USB:DADDR)
147
148For information about available fields see [`mod@daddr`]
149module*/
150pub type DADDR = crate::Reg<daddr::DADDRrs>;
151///
152pub mod daddr;
153/**LPMCSR (rw) register accessor:
154
155You can [`read`](crate::Reg::read) this register and get [`lpmcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpmcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
156
157See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#USB:LPMCSR)
158
159For information about available fields see [`mod@lpmcsr`]
160module*/
161pub type LPMCSR = crate::Reg<lpmcsr::LPMCSRrs>;
162///
163pub mod lpmcsr;
164/**BCDR (rw) register accessor:
165
166You can [`read`](crate::Reg::read) this register and get [`bcdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#USB:BCDR)
169
170For information about available fields see [`mod@bcdr`]
171module*/
172pub type BCDR = crate::Reg<bcdr::BCDRrs>;
173///
174pub mod bcdr;
stm32g0_staging/stm32g0b0/usb.rs

stm32g0_staging/stm32g0b0/
usb.rs
