stm32g0_staging/stm32g0b0/
tim16.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    _reserved2: [u8; 0x04],
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_5_ccmr1: [u8; 0x04],
12    _reserved6: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    rcr: RCR,
18    ccr: [CCR; 1],
19    _reserved12: [u8; 0x0c],
20    bdtr: BDTR,
21    dcr: DCR,
22    dmar: DMAR,
23    _reserved15: [u8; 0x10],
24    af1: AF1,
25    _reserved16: [u8; 0x04],
26    tisel: TISEL,
27}
28impl RegisterBlock {
29    ///0x00 - control register 1
30    #[inline(always)]
31    pub const fn cr1(&self) -> &CR1 {
32        &self.cr1
33    }
34    ///0x04 - control register 2
35    #[inline(always)]
36    pub const fn cr2(&self) -> &CR2 {
37        &self.cr2
38    }
39    ///0x0c - DMA/Interrupt enable register
40    #[inline(always)]
41    pub const fn dier(&self) -> &DIER {
42        &self.dier
43    }
44    ///0x10 - status register
45    #[inline(always)]
46    pub const fn sr(&self) -> &SR {
47        &self.sr
48    }
49    ///0x14 - event generation register
50    #[inline(always)]
51    pub const fn egr(&self) -> &EGR {
52        &self.egr
53    }
54    ///0x18 - capture/compare mode register 1 (input mode)
55    #[inline(always)]
56    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
57        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
58    }
59    ///0x18 - capture/compare mode register (output mode)
60    #[inline(always)]
61    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
62        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
63    }
64    ///0x20 - capture/compare enable register
65    #[inline(always)]
66    pub const fn ccer(&self) -> &CCER {
67        &self.ccer
68    }
69    ///0x24 - counter
70    #[inline(always)]
71    pub const fn cnt(&self) -> &CNT {
72        &self.cnt
73    }
74    ///0x28 - prescaler
75    #[inline(always)]
76    pub const fn psc(&self) -> &PSC {
77        &self.psc
78    }
79    ///0x2c - auto-reload register
80    #[inline(always)]
81    pub const fn arr(&self) -> &ARR {
82        &self.arr
83    }
84    ///0x30 - repetition counter register
85    #[inline(always)]
86    pub const fn rcr(&self) -> &RCR {
87        &self.rcr
88    }
89    ///0x34 - capture/compare register
90    ///
91    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
92    #[inline(always)]
93    pub const fn ccr(&self, n: usize) -> &CCR {
94        &self.ccr[n]
95    }
96    ///Iterator for array of:
97    ///0x34 - capture/compare register
98    #[inline(always)]
99    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
100        self.ccr.iter()
101    }
102    ///0x34 - capture/compare register
103    #[inline(always)]
104    pub const fn ccr1(&self) -> &CCR {
105        self.ccr(0)
106    }
107    ///0x44 - break and dead-time register
108    #[inline(always)]
109    pub const fn bdtr(&self) -> &BDTR {
110        &self.bdtr
111    }
112    ///0x48 - DMA control register
113    #[inline(always)]
114    pub const fn dcr(&self) -> &DCR {
115        &self.dcr
116    }
117    ///0x4c - DMA address for full transfer
118    #[inline(always)]
119    pub const fn dmar(&self) -> &DMAR {
120        &self.dmar
121    }
122    ///0x60 - TIM17 option register 1
123    #[inline(always)]
124    pub const fn af1(&self) -> &AF1 {
125        &self.af1
126    }
127    ///0x68 - input selection register
128    #[inline(always)]
129    pub const fn tisel(&self) -> &TISEL {
130        &self.tisel
131    }
132}
133/**CR1 (rw) register accessor: control register 1
134
135You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
136
137See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:CR1)
138
139For information about available fields see [`mod@cr1`]
140module*/
141pub type CR1 = crate::Reg<cr1::CR1rs>;
142///control register 1
143pub mod cr1;
144/**CR2 (rw) register accessor: control register 2
145
146You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
147
148See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:CR2)
149
150For information about available fields see [`mod@cr2`]
151module*/
152pub type CR2 = crate::Reg<cr2::CR2rs>;
153///control register 2
154pub mod cr2;
155/**DIER (rw) register accessor: DMA/Interrupt enable register
156
157You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
158
159See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:DIER)
160
161For information about available fields see [`mod@dier`]
162module*/
163pub type DIER = crate::Reg<dier::DIERrs>;
164///DMA/Interrupt enable register
165pub mod dier;
166/**SR (rw) register accessor: status register
167
168You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
169
170See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:SR)
171
172For information about available fields see [`mod@sr`]
173module*/
174pub type SR = crate::Reg<sr::SRrs>;
175///status register
176pub mod sr;
177/**EGR (w) register accessor: event generation register
178
179You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
180
181See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:EGR)
182
183For information about available fields see [`mod@egr`]
184module*/
185pub type EGR = crate::Reg<egr::EGRrs>;
186///event generation register
187pub mod egr;
188/**CCMR1_Output (rw) register accessor: capture/compare mode register (output mode)
189
190You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
191
192See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:CCMR1_Output)
193
194For information about available fields see [`mod@ccmr1_output`]
195module*/
196#[doc(alias = "CCMR1_Output")]
197pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
198///capture/compare mode register (output mode)
199pub mod ccmr1_output;
200/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
201
202You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
203
204See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:CCMR1_Input)
205
206For information about available fields see [`mod@ccmr1_input`]
207module*/
208#[doc(alias = "CCMR1_Input")]
209pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
210///capture/compare mode register 1 (input mode)
211pub mod ccmr1_input;
212/**CCER (rw) register accessor: capture/compare enable register
213
214You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
215
216See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:CCER)
217
218For information about available fields see [`mod@ccer`]
219module*/
220pub type CCER = crate::Reg<ccer::CCERrs>;
221///capture/compare enable register
222pub mod ccer;
223/**CNT (rw) register accessor: counter
224
225You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
226
227See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:CNT)
228
229For information about available fields see [`mod@cnt`]
230module*/
231pub type CNT = crate::Reg<cnt::CNTrs>;
232///counter
233pub mod cnt;
234/**PSC (rw) register accessor: prescaler
235
236You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
237
238See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:PSC)
239
240For information about available fields see [`mod@psc`]
241module*/
242pub type PSC = crate::Reg<psc::PSCrs>;
243///prescaler
244pub mod psc;
245/**ARR (rw) register accessor: auto-reload register
246
247You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
248
249See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:ARR)
250
251For information about available fields see [`mod@arr`]
252module*/
253pub type ARR = crate::Reg<arr::ARRrs>;
254///auto-reload register
255pub mod arr;
256/**RCR (rw) register accessor: repetition counter register
257
258You can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
259
260See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:RCR)
261
262For information about available fields see [`mod@rcr`]
263module*/
264pub type RCR = crate::Reg<rcr::RCRrs>;
265///repetition counter register
266pub mod rcr;
267/**CCR (rw) register accessor: capture/compare register
268
269You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
270
271See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:CCR[1])
272
273For information about available fields see [`mod@ccr`]
274module*/
275pub type CCR = crate::Reg<ccr::CCRrs>;
276///capture/compare register
277pub mod ccr;
278/**BDTR (rw) register accessor: break and dead-time register
279
280You can [`read`](crate::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
281
282See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:BDTR)
283
284For information about available fields see [`mod@bdtr`]
285module*/
286pub type BDTR = crate::Reg<bdtr::BDTRrs>;
287///break and dead-time register
288pub mod bdtr;
289/**DCR (rw) register accessor: DMA control register
290
291You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
292
293See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:DCR)
294
295For information about available fields see [`mod@dcr`]
296module*/
297pub type DCR = crate::Reg<dcr::DCRrs>;
298///DMA control register
299pub mod dcr;
300/**DMAR (rw) register accessor: DMA address for full transfer
301
302You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
303
304See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:DMAR)
305
306For information about available fields see [`mod@dmar`]
307module*/
308pub type DMAR = crate::Reg<dmar::DMARrs>;
309///DMA address for full transfer
310pub mod dmar;
311/**AF1 (rw) register accessor: TIM17 option register 1
312
313You can [`read`](crate::Reg::read) this register and get [`af1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`af1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
314
315See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:AF1)
316
317For information about available fields see [`mod@af1`]
318module*/
319pub type AF1 = crate::Reg<af1::AF1rs>;
320///TIM17 option register 1
321pub mod af1;
322/**TISEL (rw) register accessor: input selection register
323
324You can [`read`](crate::Reg::read) this register and get [`tisel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
325
326See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:TISEL)
327
328For information about available fields see [`mod@tisel`]
329module*/
330pub type TISEL = crate::Reg<tisel::TISELrs>;
331///input selection register
332pub mod tisel;
stm32g0_staging/stm32g0b0/tim16.rs

stm32g0_staging/stm32g0b0/
tim16.rs
