stm32g0_staging/stm32g0b0/
tim15.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved7: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    rcr: RCR,
18    ccr: [CCR; 2],
19    _reserved13: [u8; 0x08],
20    bdtr: BDTR,
21    dcr: DCR,
22    dmar: DMAR,
23    _reserved16: [u8; 0x10],
24    af1: AF1,
25    _reserved17: [u8; 0x04],
26    tisel: TISEL,
27}
28impl RegisterBlock {
29    ///0x00 - control register 1
30    #[inline(always)]
31    pub const fn cr1(&self) -> &CR1 {
32        &self.cr1
33    }
34    ///0x04 - control register 2
35    #[inline(always)]
36    pub const fn cr2(&self) -> &CR2 {
37        &self.cr2
38    }
39    ///0x08 - slave mode control register
40    #[inline(always)]
41    pub const fn smcr(&self) -> &SMCR {
42        &self.smcr
43    }
44    ///0x0c - DMA/Interrupt enable register
45    #[inline(always)]
46    pub const fn dier(&self) -> &DIER {
47        &self.dier
48    }
49    ///0x10 - status register
50    #[inline(always)]
51    pub const fn sr(&self) -> &SR {
52        &self.sr
53    }
54    ///0x14 - event generation register
55    #[inline(always)]
56    pub const fn egr(&self) -> &EGR {
57        &self.egr
58    }
59    ///0x18 - capture/compare mode register 1 (input mode)
60    #[inline(always)]
61    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
62        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
63    }
64    ///0x18 - capture/compare mode register (output mode)
65    #[inline(always)]
66    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
67        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
68    }
69    ///0x20 - capture/compare enable register
70    #[inline(always)]
71    pub const fn ccer(&self) -> &CCER {
72        &self.ccer
73    }
74    ///0x24 - counter
75    #[inline(always)]
76    pub const fn cnt(&self) -> &CNT {
77        &self.cnt
78    }
79    ///0x28 - prescaler
80    #[inline(always)]
81    pub const fn psc(&self) -> &PSC {
82        &self.psc
83    }
84    ///0x2c - auto-reload register
85    #[inline(always)]
86    pub const fn arr(&self) -> &ARR {
87        &self.arr
88    }
89    ///0x30 - repetition counter register
90    #[inline(always)]
91    pub const fn rcr(&self) -> &RCR {
92        &self.rcr
93    }
94    ///0x34..0x3c - capture/compare register
95    ///
96    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
97    #[inline(always)]
98    pub const fn ccr(&self, n: usize) -> &CCR {
99        &self.ccr[n]
100    }
101    ///Iterator for array of:
102    ///0x34..0x3c - capture/compare register
103    #[inline(always)]
104    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
105        self.ccr.iter()
106    }
107    ///0x34 - capture/compare register
108    #[inline(always)]
109    pub const fn ccr1(&self) -> &CCR {
110        self.ccr(0)
111    }
112    ///0x38 - capture/compare register
113    #[inline(always)]
114    pub const fn ccr2(&self) -> &CCR {
115        self.ccr(1)
116    }
117    ///0x44 - break and dead-time register
118    #[inline(always)]
119    pub const fn bdtr(&self) -> &BDTR {
120        &self.bdtr
121    }
122    ///0x48 - DMA control register
123    #[inline(always)]
124    pub const fn dcr(&self) -> &DCR {
125        &self.dcr
126    }
127    ///0x4c - DMA address for full transfer
128    #[inline(always)]
129    pub const fn dmar(&self) -> &DMAR {
130        &self.dmar
131    }
132    ///0x60 - TIM15 alternate register 1
133    #[inline(always)]
134    pub const fn af1(&self) -> &AF1 {
135        &self.af1
136    }
137    ///0x68 - input selection register
138    #[inline(always)]
139    pub const fn tisel(&self) -> &TISEL {
140        &self.tisel
141    }
142}
143/**CR1 (rw) register accessor: control register 1
144
145You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
146
147See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:CR1)
148
149For information about available fields see [`mod@cr1`]
150module*/
151pub type CR1 = crate::Reg<cr1::CR1rs>;
152///control register 1
153pub mod cr1;
154/**CR2 (rw) register accessor: control register 2
155
156You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
157
158See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:CR2)
159
160For information about available fields see [`mod@cr2`]
161module*/
162pub type CR2 = crate::Reg<cr2::CR2rs>;
163///control register 2
164pub mod cr2;
165/**SMCR (rw) register accessor: slave mode control register
166
167You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
168
169See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:SMCR)
170
171For information about available fields see [`mod@smcr`]
172module*/
173pub type SMCR = crate::Reg<smcr::SMCRrs>;
174///slave mode control register
175pub mod smcr;
176/**DIER (rw) register accessor: DMA/Interrupt enable register
177
178You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
179
180See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:DIER)
181
182For information about available fields see [`mod@dier`]
183module*/
184pub type DIER = crate::Reg<dier::DIERrs>;
185///DMA/Interrupt enable register
186pub mod dier;
187/**SR (rw) register accessor: status register
188
189You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
190
191See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:SR)
192
193For information about available fields see [`mod@sr`]
194module*/
195pub type SR = crate::Reg<sr::SRrs>;
196///status register
197pub mod sr;
198/**EGR (w) register accessor: event generation register
199
200You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
201
202See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:EGR)
203
204For information about available fields see [`mod@egr`]
205module*/
206pub type EGR = crate::Reg<egr::EGRrs>;
207///event generation register
208pub mod egr;
209/**CCMR1_Output (rw) register accessor: capture/compare mode register (output mode)
210
211You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
212
213See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:CCMR1_Output)
214
215For information about available fields see [`mod@ccmr1_output`]
216module*/
217#[doc(alias = "CCMR1_Output")]
218pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
219///capture/compare mode register (output mode)
220pub mod ccmr1_output;
221/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
222
223You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
224
225See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:CCMR1_Input)
226
227For information about available fields see [`mod@ccmr1_input`]
228module*/
229#[doc(alias = "CCMR1_Input")]
230pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
231///capture/compare mode register 1 (input mode)
232pub mod ccmr1_input;
233/**CCER (rw) register accessor: capture/compare enable register
234
235You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
236
237See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:CCER)
238
239For information about available fields see [`mod@ccer`]
240module*/
241pub type CCER = crate::Reg<ccer::CCERrs>;
242///capture/compare enable register
243pub mod ccer;
244/**CNT (rw) register accessor: counter
245
246You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
247
248See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:CNT)
249
250For information about available fields see [`mod@cnt`]
251module*/
252pub type CNT = crate::Reg<cnt::CNTrs>;
253///counter
254pub mod cnt;
255/**PSC (rw) register accessor: prescaler
256
257You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
258
259See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:PSC)
260
261For information about available fields see [`mod@psc`]
262module*/
263pub type PSC = crate::Reg<psc::PSCrs>;
264///prescaler
265pub mod psc;
266/**ARR (rw) register accessor: auto-reload register
267
268You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
269
270See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:ARR)
271
272For information about available fields see [`mod@arr`]
273module*/
274pub type ARR = crate::Reg<arr::ARRrs>;
275///auto-reload register
276pub mod arr;
277/**RCR (rw) register accessor: repetition counter register
278
279You can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
280
281See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:RCR)
282
283For information about available fields see [`mod@rcr`]
284module*/
285pub type RCR = crate::Reg<rcr::RCRrs>;
286///repetition counter register
287pub mod rcr;
288/**CCR (rw) register accessor: capture/compare register
289
290You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
291
292See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:CCR[1])
293
294For information about available fields see [`mod@ccr`]
295module*/
296pub type CCR = crate::Reg<ccr::CCRrs>;
297///capture/compare register
298pub mod ccr;
299/**BDTR (rw) register accessor: break and dead-time register
300
301You can [`read`](crate::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
302
303See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:BDTR)
304
305For information about available fields see [`mod@bdtr`]
306module*/
307pub type BDTR = crate::Reg<bdtr::BDTRrs>;
308///break and dead-time register
309pub mod bdtr;
310/**DCR (rw) register accessor: DMA control register
311
312You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
313
314See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:DCR)
315
316For information about available fields see [`mod@dcr`]
317module*/
318pub type DCR = crate::Reg<dcr::DCRrs>;
319///DMA control register
320pub mod dcr;
321/**DMAR (rw) register accessor: DMA address for full transfer
322
323You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
324
325See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:DMAR)
326
327For information about available fields see [`mod@dmar`]
328module*/
329pub type DMAR = crate::Reg<dmar::DMARrs>;
330///DMA address for full transfer
331pub mod dmar;
332/**AF1 (rw) register accessor: TIM15 alternate register 1
333
334You can [`read`](crate::Reg::read) this register and get [`af1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`af1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
335
336See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:AF1)
337
338For information about available fields see [`mod@af1`]
339module*/
340pub type AF1 = crate::Reg<af1::AF1rs>;
341///TIM15 alternate register 1
342pub mod af1;
343/**TISEL (rw) register accessor: input selection register
344
345You can [`read`](crate::Reg::read) this register and get [`tisel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
346
347See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM15:TISEL)
348
349For information about available fields see [`mod@tisel`]
350module*/
351pub type TISEL = crate::Reg<tisel::TISELrs>;
352///input selection register
353pub mod tisel;
stm32g0_staging/stm32g0b0/tim15.rs

stm32g0_staging/stm32g0b0/
tim15.rs
