stm32g0_staging/stm32g0b0/spi1/
dr.rs

1///Register `DR` reader
2pub type R = crate::R<DRrs>;
3///Register `DR` writer
4pub type W = crate::W<DRrs>;
5///Field `DR` reader - Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used.
6pub type DR_R = crate::FieldReader<u16>;
7///Field `DR` writer - Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used.
8pub type DR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16, crate::Safe>;
9impl R {
10    ///Bits 0:15 - Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used.
11    #[inline(always)]
12    pub fn dr(&self) -> DR_R {
13        DR_R::new(self.bits)
14    }
15}
16impl core::fmt::Debug for R {
17    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
18        f.debug_struct("DR").field("dr", &self.dr()).finish()
19    }
20}
21impl W {
22    ///Bits 0:15 - Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used.
23    #[inline(always)]
24    pub fn dr(&mut self) -> DR_W<DRrs> {
25        DR_W::new(self, 0)
26    }
27}
28/**
29
30You can [`read`](crate::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
31
32See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:DR)*/
33pub struct DRrs;
34impl crate::RegisterSpec for DRrs {
35    type Ux = u16;
36}
37///`read()` method returns [`dr::R`](R) reader structure
38impl crate::Readable for DRrs {}
39///`write(|w| ..)` method takes [`dr::W`](W) writer structure
40impl crate::Writable for DRrs {
41    type Safety = crate::Safe;
42    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
43    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
44}
45///`reset()` method sets DR to value 0
46impl crate::Resettable for DRrs {
47    const RESET_VALUE: u16 = 0;
48}
stm32g0_staging/stm32g0b0/spi1/dr.rs

stm32g0_staging/stm32g0b0/spi1/
dr.rs
