stm32g0_staging/stm32g0b0/
spi1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    _reserved1: [u8; 0x02],
7    cr2: CR2,
8    _reserved2: [u8; 0x02],
9    sr: SR,
10    _reserved3: [u8; 0x02],
11    _reserved_3_dr: [u8; 0x02],
12    _reserved4: [u8; 0x02],
13    crcpr: CRCPR,
14    _reserved5: [u8; 0x02],
15    rxcrcr: RXCRCR,
16    _reserved6: [u8; 0x02],
17    txcrcr: TXCRCR,
18    _reserved7: [u8; 0x02],
19    i2scfgr: I2SCFGR,
20    _reserved8: [u8; 0x02],
21    i2spr: I2SPR,
22}
23impl RegisterBlock {
24    ///0x00 -
25    #[inline(always)]
26    pub const fn cr1(&self) -> &CR1 {
27        &self.cr1
28    }
29    ///0x04 -
30    #[inline(always)]
31    pub const fn cr2(&self) -> &CR2 {
32        &self.cr2
33    }
34    ///0x08 -
35    #[inline(always)]
36    pub const fn sr(&self) -> &SR {
37        &self.sr
38    }
39    ///0x0c - Direct 8-bit access to data register
40    #[inline(always)]
41    pub const fn dr8(&self) -> &DR8 {
42        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
43    }
44    ///0x0c -
45    #[inline(always)]
46    pub const fn dr(&self) -> &DR {
47        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
48    }
49    ///0x10 -
50    #[inline(always)]
51    pub const fn crcpr(&self) -> &CRCPR {
52        &self.crcpr
53    }
54    ///0x14 -
55    #[inline(always)]
56    pub const fn rxcrcr(&self) -> &RXCRCR {
57        &self.rxcrcr
58    }
59    ///0x18 -
60    #[inline(always)]
61    pub const fn txcrcr(&self) -> &TXCRCR {
62        &self.txcrcr
63    }
64    ///0x1c -
65    #[inline(always)]
66    pub const fn i2scfgr(&self) -> &I2SCFGR {
67        &self.i2scfgr
68    }
69    ///0x20 -
70    #[inline(always)]
71    pub const fn i2spr(&self) -> &I2SPR {
72        &self.i2spr
73    }
74}
75/**CR1 (rw) register accessor:
76
77You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:CR1)
80
81For information about available fields see [`mod@cr1`]
82module*/
83pub type CR1 = crate::Reg<cr1::CR1rs>;
84///
85pub mod cr1;
86/**CR2 (rw) register accessor:
87
88You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
89
90See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:CR2)
91
92For information about available fields see [`mod@cr2`]
93module*/
94pub type CR2 = crate::Reg<cr2::CR2rs>;
95///
96pub mod cr2;
97/**SR (rw) register accessor:
98
99You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
100
101See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:SR)
102
103For information about available fields see [`mod@sr`]
104module*/
105pub type SR = crate::Reg<sr::SRrs>;
106///
107pub mod sr;
108/**DR (rw) register accessor:
109
110You can [`read`](crate::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
111
112See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:DR)
113
114For information about available fields see [`mod@dr`]
115module*/
116pub type DR = crate::Reg<dr::DRrs>;
117///
118pub mod dr;
119/**CRCPR (rw) register accessor:
120
121You can [`read`](crate::Reg::read) this register and get [`crcpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crcpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
122
123See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:CRCPR)
124
125For information about available fields see [`mod@crcpr`]
126module*/
127pub type CRCPR = crate::Reg<crcpr::CRCPRrs>;
128///
129pub mod crcpr;
130/**RXCRCR (r) register accessor:
131
132You can [`read`](crate::Reg::read) this register and get [`rxcrcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
133
134See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:RXCRCR)
135
136For information about available fields see [`mod@rxcrcr`]
137module*/
138pub type RXCRCR = crate::Reg<rxcrcr::RXCRCRrs>;
139///
140pub mod rxcrcr;
141/**TXCRCR (r) register accessor:
142
143You can [`read`](crate::Reg::read) this register and get [`txcrcr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
144
145See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:TXCRCR)
146
147For information about available fields see [`mod@txcrcr`]
148module*/
149pub type TXCRCR = crate::Reg<txcrcr::TXCRCRrs>;
150///
151pub mod txcrcr;
152/**I2SCFGR (rw) register accessor:
153
154You can [`read`](crate::Reg::read) this register and get [`i2scfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2scfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
155
156See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:I2SCFGR)
157
158For information about available fields see [`mod@i2scfgr`]
159module*/
160pub type I2SCFGR = crate::Reg<i2scfgr::I2SCFGRrs>;
161///
162pub mod i2scfgr;
163/**I2SPR (rw) register accessor:
164
165You can [`read`](crate::Reg::read) this register and get [`i2spr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2spr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
166
167See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:I2SPR)
168
169For information about available fields see [`mod@i2spr`]
170module*/
171pub type I2SPR = crate::Reg<i2spr::I2SPRrs>;
172///
173pub mod i2spr;
174/**DR8 (rw) register accessor: Direct 8-bit access to data register
175
176You can [`read`](crate::Reg::read) this register and get [`dr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
177
178See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#SPI1:DR8)
179
180For information about available fields see [`mod@dr8`]
181module*/
182pub type DR8 = crate::Reg<dr8::DR8rs>;
183///Direct 8-bit access to data register
184pub mod dr8;
stm32g0_staging/stm32g0b0/spi1.rs

stm32g0_staging/stm32g0b0/
spi1.rs
