stm32g0_staging/stm32g0b0/rtc/
shiftr.rs

1///Register `SHIFTR` writer
2pub type W = crate::W<SHIFTRrs>;
3///Field `SUBFS` writer - Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time.
4pub type SUBFS_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16, crate::Safe>;
5/**Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum ADD1SW {
11    ///1: Add one second to the clock/calendar
12    Add1 = 1,
13}
14impl From<ADD1SW> for bool {
15    #[inline(always)]
16    fn from(variant: ADD1SW) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `ADD1S` writer - Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.
21pub type ADD1S_W<'a, REG> = crate::BitWriter<'a, REG, ADD1SW>;
22impl<'a, REG> ADD1S_W<'a, REG>
23where
24    REG: crate::Writable + crate::RegisterSpec,
25{
26    ///Add one second to the clock/calendar
27    #[inline(always)]
28    pub fn add1(self) -> &'a mut crate::W<REG> {
29        self.variant(ADD1SW::Add1)
30    }
31}
32impl core::fmt::Debug for crate::generic::Reg<SHIFTRrs> {
33    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
34        write!(f, "(not readable)")
35    }
36}
37impl W {
38    ///Bits 0:14 - Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time.
39    #[inline(always)]
40    pub fn subfs(&mut self) -> SUBFS_W<SHIFTRrs> {
41        SUBFS_W::new(self, 0)
42    }
43    ///Bit 31 - Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.
44    #[inline(always)]
45    pub fn add1s(&mut self) -> ADD1S_W<SHIFTRrs> {
46        ADD1S_W::new(self, 31)
47    }
48}
49/**RTC shift control register
50
51You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
52
53See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RTC:SHIFTR)*/
54pub struct SHIFTRrs;
55impl crate::RegisterSpec for SHIFTRrs {
56    type Ux = u32;
57}
58///`write(|w| ..)` method takes [`shiftr::W`](W) writer structure
59impl crate::Writable for SHIFTRrs {
60    type Safety = crate::Unsafe;
61    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
63}
64///`reset()` method sets SHIFTR to value 0
65impl crate::Resettable for SHIFTRrs {
66    const RESET_VALUE: u32 = 0;
67}
stm32g0_staging/stm32g0b0/rtc/shiftr.rs

stm32g0_staging/stm32g0b0/rtc/
shiftr.rs
