stm32g0_staging/stm32g0b0/rtc/
scr.rs

1///Register `SCR` writer
2pub type W = crate::W<SCRrs>;
3/**Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register.
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum CALRAF {
9    ///1: Clear interrupt flag by writing 1
10    Clear = 1,
11}
12impl From<CALRAF> for bool {
13    #[inline(always)]
14    fn from(variant: CALRAF) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `CALRAF` writer - Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register.
19pub type CALRAF_W<'a, REG> = crate::BitWriter<'a, REG, CALRAF>;
20impl<'a, REG> CALRAF_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Clear interrupt flag by writing 1
25    #[inline(always)]
26    pub fn clear(self) -> &'a mut crate::W<REG> {
27        self.variant(CALRAF::Clear)
28    }
29}
30///Field `CALRBF` writer - Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.
31pub use CALRAF_W as CALRBF_W;
32///Field `CWUTF` writer - Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register.
33pub use CALRAF_W as CWUTF_W;
34///Field `CTSF` writer - Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF.
35pub use CALRAF_W as CTSF_W;
36///Field `CTSOVF` writer - Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
37pub use CALRAF_W as CTSOVF_W;
38///Field `CITSF` writer - Clear internal timestamp flag Writing 1 in this bit clears the ITSF bit in the RTC_SR register.
39pub use CALRAF_W as CITSF_W;
40impl core::fmt::Debug for crate::generic::Reg<SCRrs> {
41    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
42        write!(f, "(not readable)")
43    }
44}
45impl W {
46    ///Bit 0 - Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register.
47    #[inline(always)]
48    pub fn calraf(&mut self) -> CALRAF_W<SCRrs> {
49        CALRAF_W::new(self, 0)
50    }
51    ///Bit 1 - Clear alarm B flag Writing 1 in this bit clears the ALRBF bit in the RTC_SR register.
52    #[inline(always)]
53    pub fn calrbf(&mut self) -> CALRBF_W<SCRrs> {
54        CALRBF_W::new(self, 1)
55    }
56    ///Bit 2 - Clear wakeup timer flag Writing 1 in this bit clears the WUTF bit in the RTC_SR register.
57    #[inline(always)]
58    pub fn cwutf(&mut self) -> CWUTF_W<SCRrs> {
59        CWUTF_W::new(self, 2)
60    }
61    ///Bit 3 - Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. If ITSF flag is set, TSF must be cleared together with ITSF by setting CRSF and CITSF.
62    #[inline(always)]
63    pub fn ctsf(&mut self) -> CTSF_W<SCRrs> {
64        CTSF_W::new(self, 3)
65    }
66    ///Bit 4 - Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
67    #[inline(always)]
68    pub fn ctsovf(&mut self) -> CTSOVF_W<SCRrs> {
69        CTSOVF_W::new(self, 4)
70    }
71    ///Bit 5 - Clear internal timestamp flag Writing 1 in this bit clears the ITSF bit in the RTC_SR register.
72    #[inline(always)]
73    pub fn citsf(&mut self) -> CITSF_W<SCRrs> {
74        CITSF_W::new(self, 5)
75    }
76}
77/**RTC status clear register
78
79You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
80
81See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RTC:SCR)*/
82pub struct SCRrs;
83impl crate::RegisterSpec for SCRrs {
84    type Ux = u32;
85}
86///`write(|w| ..)` method takes [`scr::W`](W) writer structure
87impl crate::Writable for SCRrs {
88    type Safety = crate::Unsafe;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91}
92///`reset()` method sets SCR to value 0
93impl crate::Resettable for SCRrs {
94    const RESET_VALUE: u32 = 0;
95}
stm32g0_staging/stm32g0b0/rtc/scr.rs

stm32g0_staging/stm32g0b0/rtc/
scr.rs
