stm32g0_staging/stm32g0b0/rtc/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**ck_wut wakeup clock selection 10x: ck_spre (usually 1Hz) clock is selected 11x: ck_spre (usually 1Hz) clock is selected and 216is added to the WUT counter value
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum WUCKSEL {
12    ///0: RTC/16 clock is selected
13    Div16 = 0,
14    ///1: RTC/8 clock is selected
15    Div8 = 1,
16    ///2: RTC/4 clock is selected
17    Div4 = 2,
18    ///3: RTC/2 clock is selected
19    Div2 = 3,
20    ///4: ck_spre (usually 1 Hz) clock is selected
21    ClockSpare = 4,
22    ///6: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
23    ClockSpareWithOffset = 6,
24}
25impl From<WUCKSEL> for u8 {
26    #[inline(always)]
27    fn from(variant: WUCKSEL) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for WUCKSEL {
32    type Ux = u8;
33}
34impl crate::IsEnum for WUCKSEL {}
35///Field `WUCKSEL` reader - ck_wut wakeup clock selection 10x: ck_spre (usually 1Hz) clock is selected 11x: ck_spre (usually 1Hz) clock is selected and 216is added to the WUT counter value
36pub type WUCKSEL_R = crate::FieldReader<WUCKSEL>;
37impl WUCKSEL_R {
38    ///Get enumerated values variant
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<WUCKSEL> {
41        match self.bits {
42            0 => Some(WUCKSEL::Div16),
43            1 => Some(WUCKSEL::Div8),
44            2 => Some(WUCKSEL::Div4),
45            3 => Some(WUCKSEL::Div2),
46            4 => Some(WUCKSEL::ClockSpare),
47            6 => Some(WUCKSEL::ClockSpareWithOffset),
48            _ => None,
49        }
50    }
51    ///RTC/16 clock is selected
52    #[inline(always)]
53    pub fn is_div16(&self) -> bool {
54        *self == WUCKSEL::Div16
55    }
56    ///RTC/8 clock is selected
57    #[inline(always)]
58    pub fn is_div8(&self) -> bool {
59        *self == WUCKSEL::Div8
60    }
61    ///RTC/4 clock is selected
62    #[inline(always)]
63    pub fn is_div4(&self) -> bool {
64        *self == WUCKSEL::Div4
65    }
66    ///RTC/2 clock is selected
67    #[inline(always)]
68    pub fn is_div2(&self) -> bool {
69        *self == WUCKSEL::Div2
70    }
71    ///ck_spre (usually 1 Hz) clock is selected
72    #[inline(always)]
73    pub fn is_clock_spare(&self) -> bool {
74        *self == WUCKSEL::ClockSpare
75    }
76    ///ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
77    #[inline(always)]
78    pub fn is_clock_spare_with_offset(&self) -> bool {
79        *self == WUCKSEL::ClockSpareWithOffset
80    }
81}
82///Field `WUCKSEL` writer - ck_wut wakeup clock selection 10x: ck_spre (usually 1Hz) clock is selected 11x: ck_spre (usually 1Hz) clock is selected and 216is added to the WUT counter value
83pub type WUCKSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, WUCKSEL>;
84impl<'a, REG> WUCKSEL_W<'a, REG>
85where
86    REG: crate::Writable + crate::RegisterSpec,
87    REG::Ux: From<u8>,
88{
89    ///RTC/16 clock is selected
90    #[inline(always)]
91    pub fn div16(self) -> &'a mut crate::W<REG> {
92        self.variant(WUCKSEL::Div16)
93    }
94    ///RTC/8 clock is selected
95    #[inline(always)]
96    pub fn div8(self) -> &'a mut crate::W<REG> {
97        self.variant(WUCKSEL::Div8)
98    }
99    ///RTC/4 clock is selected
100    #[inline(always)]
101    pub fn div4(self) -> &'a mut crate::W<REG> {
102        self.variant(WUCKSEL::Div4)
103    }
104    ///RTC/2 clock is selected
105    #[inline(always)]
106    pub fn div2(self) -> &'a mut crate::W<REG> {
107        self.variant(WUCKSEL::Div2)
108    }
109    ///ck_spre (usually 1 Hz) clock is selected
110    #[inline(always)]
111    pub fn clock_spare(self) -> &'a mut crate::W<REG> {
112        self.variant(WUCKSEL::ClockSpare)
113    }
114    ///ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value
115    #[inline(always)]
116    pub fn clock_spare_with_offset(self) -> &'a mut crate::W<REG> {
117        self.variant(WUCKSEL::ClockSpareWithOffset)
118    }
119}
120/**Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
121
122Value on reset: 0*/
123#[cfg_attr(feature = "defmt", derive(defmt::Format))]
124#[derive(Clone, Copy, Debug, PartialEq, Eq)]
125pub enum TSEDGE {
126    ///0: RTC_TS input rising edge generates a time-stamp event
127    RisingEdge = 0,
128    ///1: RTC_TS input falling edge generates a time-stamp event
129    FallingEdge = 1,
130}
131impl From<TSEDGE> for bool {
132    #[inline(always)]
133    fn from(variant: TSEDGE) -> Self {
134        variant as u8 != 0
135    }
136}
137///Field `TSEDGE` reader - Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
138pub type TSEDGE_R = crate::BitReader<TSEDGE>;
139impl TSEDGE_R {
140    ///Get enumerated values variant
141    #[inline(always)]
142    pub const fn variant(&self) -> TSEDGE {
143        match self.bits {
144            false => TSEDGE::RisingEdge,
145            true => TSEDGE::FallingEdge,
146        }
147    }
148    ///RTC_TS input rising edge generates a time-stamp event
149    #[inline(always)]
150    pub fn is_rising_edge(&self) -> bool {
151        *self == TSEDGE::RisingEdge
152    }
153    ///RTC_TS input falling edge generates a time-stamp event
154    #[inline(always)]
155    pub fn is_falling_edge(&self) -> bool {
156        *self == TSEDGE::FallingEdge
157    }
158}
159///Field `TSEDGE` writer - Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
160pub type TSEDGE_W<'a, REG> = crate::BitWriter<'a, REG, TSEDGE>;
161impl<'a, REG> TSEDGE_W<'a, REG>
162where
163    REG: crate::Writable + crate::RegisterSpec,
164{
165    ///RTC_TS input rising edge generates a time-stamp event
166    #[inline(always)]
167    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
168        self.variant(TSEDGE::RisingEdge)
169    }
170    ///RTC_TS input falling edge generates a time-stamp event
171    #[inline(always)]
172    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
173        self.variant(TSEDGE::FallingEdge)
174    }
175}
176/**RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF.
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum REFCKON {
182    ///0: RTC_REFIN detection disabled
183    Disabled = 0,
184    ///1: RTC_REFIN detection enabled
185    Enabled = 1,
186}
187impl From<REFCKON> for bool {
188    #[inline(always)]
189    fn from(variant: REFCKON) -> Self {
190        variant as u8 != 0
191    }
192}
193///Field `REFCKON` reader - RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF.
194pub type REFCKON_R = crate::BitReader<REFCKON>;
195impl REFCKON_R {
196    ///Get enumerated values variant
197    #[inline(always)]
198    pub const fn variant(&self) -> REFCKON {
199        match self.bits {
200            false => REFCKON::Disabled,
201            true => REFCKON::Enabled,
202        }
203    }
204    ///RTC_REFIN detection disabled
205    #[inline(always)]
206    pub fn is_disabled(&self) -> bool {
207        *self == REFCKON::Disabled
208    }
209    ///RTC_REFIN detection enabled
210    #[inline(always)]
211    pub fn is_enabled(&self) -> bool {
212        *self == REFCKON::Enabled
213    }
214}
215///Field `REFCKON` writer - RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF.
216pub type REFCKON_W<'a, REG> = crate::BitWriter<'a, REG, REFCKON>;
217impl<'a, REG> REFCKON_W<'a, REG>
218where
219    REG: crate::Writable + crate::RegisterSpec,
220{
221    ///RTC_REFIN detection disabled
222    #[inline(always)]
223    pub fn disabled(self) -> &'a mut crate::W<REG> {
224        self.variant(REFCKON::Disabled)
225    }
226    ///RTC_REFIN detection enabled
227    #[inline(always)]
228    pub fn enabled(self) -> &'a mut crate::W<REG> {
229        self.variant(REFCKON::Enabled)
230    }
231}
232/**Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
233
234Value on reset: 0*/
235#[cfg_attr(feature = "defmt", derive(defmt::Format))]
236#[derive(Clone, Copy, Debug, PartialEq, Eq)]
237pub enum BYPSHAD {
238    ///0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
239    ShadowReg = 0,
240    ///1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
241    BypassShadowReg = 1,
242}
243impl From<BYPSHAD> for bool {
244    #[inline(always)]
245    fn from(variant: BYPSHAD) -> Self {
246        variant as u8 != 0
247    }
248}
249///Field `BYPSHAD` reader - Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
250pub type BYPSHAD_R = crate::BitReader<BYPSHAD>;
251impl BYPSHAD_R {
252    ///Get enumerated values variant
253    #[inline(always)]
254    pub const fn variant(&self) -> BYPSHAD {
255        match self.bits {
256            false => BYPSHAD::ShadowReg,
257            true => BYPSHAD::BypassShadowReg,
258        }
259    }
260    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
261    #[inline(always)]
262    pub fn is_shadow_reg(&self) -> bool {
263        *self == BYPSHAD::ShadowReg
264    }
265    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
266    #[inline(always)]
267    pub fn is_bypass_shadow_reg(&self) -> bool {
268        *self == BYPSHAD::BypassShadowReg
269    }
270}
271///Field `BYPSHAD` writer - Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
272pub type BYPSHAD_W<'a, REG> = crate::BitWriter<'a, REG, BYPSHAD>;
273impl<'a, REG> BYPSHAD_W<'a, REG>
274where
275    REG: crate::Writable + crate::RegisterSpec,
276{
277    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
278    #[inline(always)]
279    pub fn shadow_reg(self) -> &'a mut crate::W<REG> {
280        self.variant(BYPSHAD::ShadowReg)
281    }
282    ///Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters
283    #[inline(always)]
284    pub fn bypass_shadow_reg(self) -> &'a mut crate::W<REG> {
285        self.variant(BYPSHAD::BypassShadowReg)
286    }
287}
288/**Hour format
289
290Value on reset: 0*/
291#[cfg_attr(feature = "defmt", derive(defmt::Format))]
292#[derive(Clone, Copy, Debug, PartialEq, Eq)]
293pub enum FMT {
294    ///0: 24 hour/day format
295    TwentyFourHour = 0,
296    ///1: AM/PM hour format
297    AmPm = 1,
298}
299impl From<FMT> for bool {
300    #[inline(always)]
301    fn from(variant: FMT) -> Self {
302        variant as u8 != 0
303    }
304}
305///Field `FMT` reader - Hour format
306pub type FMT_R = crate::BitReader<FMT>;
307impl FMT_R {
308    ///Get enumerated values variant
309    #[inline(always)]
310    pub const fn variant(&self) -> FMT {
311        match self.bits {
312            false => FMT::TwentyFourHour,
313            true => FMT::AmPm,
314        }
315    }
316    ///24 hour/day format
317    #[inline(always)]
318    pub fn is_twenty_four_hour(&self) -> bool {
319        *self == FMT::TwentyFourHour
320    }
321    ///AM/PM hour format
322    #[inline(always)]
323    pub fn is_am_pm(&self) -> bool {
324        *self == FMT::AmPm
325    }
326}
327///Field `FMT` writer - Hour format
328pub type FMT_W<'a, REG> = crate::BitWriter<'a, REG, FMT>;
329impl<'a, REG> FMT_W<'a, REG>
330where
331    REG: crate::Writable + crate::RegisterSpec,
332{
333    ///24 hour/day format
334    #[inline(always)]
335    pub fn twenty_four_hour(self) -> &'a mut crate::W<REG> {
336        self.variant(FMT::TwentyFourHour)
337    }
338    ///AM/PM hour format
339    #[inline(always)]
340    pub fn am_pm(self) -> &'a mut crate::W<REG> {
341        self.variant(FMT::AmPm)
342    }
343}
344/**Alarm %s enable
345
346Value on reset: 0*/
347#[cfg_attr(feature = "defmt", derive(defmt::Format))]
348#[derive(Clone, Copy, Debug, PartialEq, Eq)]
349pub enum ALRAE {
350    ///0: Alarm A disabled
351    Disabled = 0,
352    ///1: Alarm A enabled
353    Enabled = 1,
354}
355impl From<ALRAE> for bool {
356    #[inline(always)]
357    fn from(variant: ALRAE) -> Self {
358        variant as u8 != 0
359    }
360}
361///Field `ALRE(A,B)` reader - Alarm %s enable
362pub type ALRE_R = crate::BitReader<ALRAE>;
363impl ALRE_R {
364    ///Get enumerated values variant
365    #[inline(always)]
366    pub const fn variant(&self) -> ALRAE {
367        match self.bits {
368            false => ALRAE::Disabled,
369            true => ALRAE::Enabled,
370        }
371    }
372    ///Alarm A disabled
373    #[inline(always)]
374    pub fn is_disabled(&self) -> bool {
375        *self == ALRAE::Disabled
376    }
377    ///Alarm A enabled
378    #[inline(always)]
379    pub fn is_enabled(&self) -> bool {
380        *self == ALRAE::Enabled
381    }
382}
383///Field `ALRE(A,B)` writer - Alarm %s enable
384pub type ALRE_W<'a, REG> = crate::BitWriter<'a, REG, ALRAE>;
385impl<'a, REG> ALRE_W<'a, REG>
386where
387    REG: crate::Writable + crate::RegisterSpec,
388{
389    ///Alarm A disabled
390    #[inline(always)]
391    pub fn disabled(self) -> &'a mut crate::W<REG> {
392        self.variant(ALRAE::Disabled)
393    }
394    ///Alarm A enabled
395    #[inline(always)]
396    pub fn enabled(self) -> &'a mut crate::W<REG> {
397        self.variant(ALRAE::Enabled)
398    }
399}
400/**Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
401
402Value on reset: 0*/
403#[cfg_attr(feature = "defmt", derive(defmt::Format))]
404#[derive(Clone, Copy, Debug, PartialEq, Eq)]
405pub enum WUTE {
406    ///0: Wakeup timer disabled
407    Disabled = 0,
408    ///1: Wakeup timer enabled
409    Enabled = 1,
410}
411impl From<WUTE> for bool {
412    #[inline(always)]
413    fn from(variant: WUTE) -> Self {
414        variant as u8 != 0
415    }
416}
417///Field `WUTE` reader - Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
418pub type WUTE_R = crate::BitReader<WUTE>;
419impl WUTE_R {
420    ///Get enumerated values variant
421    #[inline(always)]
422    pub const fn variant(&self) -> WUTE {
423        match self.bits {
424            false => WUTE::Disabled,
425            true => WUTE::Enabled,
426        }
427    }
428    ///Wakeup timer disabled
429    #[inline(always)]
430    pub fn is_disabled(&self) -> bool {
431        *self == WUTE::Disabled
432    }
433    ///Wakeup timer enabled
434    #[inline(always)]
435    pub fn is_enabled(&self) -> bool {
436        *self == WUTE::Enabled
437    }
438}
439///Field `WUTE` writer - Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
440pub type WUTE_W<'a, REG> = crate::BitWriter<'a, REG, WUTE>;
441impl<'a, REG> WUTE_W<'a, REG>
442where
443    REG: crate::Writable + crate::RegisterSpec,
444{
445    ///Wakeup timer disabled
446    #[inline(always)]
447    pub fn disabled(self) -> &'a mut crate::W<REG> {
448        self.variant(WUTE::Disabled)
449    }
450    ///Wakeup timer enabled
451    #[inline(always)]
452    pub fn enabled(self) -> &'a mut crate::W<REG> {
453        self.variant(WUTE::Enabled)
454    }
455}
456/**timestamp enable
457
458Value on reset: 0*/
459#[cfg_attr(feature = "defmt", derive(defmt::Format))]
460#[derive(Clone, Copy, Debug, PartialEq, Eq)]
461pub enum TSE {
462    ///0: Timestamp disabled
463    Disabled = 0,
464    ///1: Timestamp enabled
465    Enabled = 1,
466}
467impl From<TSE> for bool {
468    #[inline(always)]
469    fn from(variant: TSE) -> Self {
470        variant as u8 != 0
471    }
472}
473///Field `TSE` reader - timestamp enable
474pub type TSE_R = crate::BitReader<TSE>;
475impl TSE_R {
476    ///Get enumerated values variant
477    #[inline(always)]
478    pub const fn variant(&self) -> TSE {
479        match self.bits {
480            false => TSE::Disabled,
481            true => TSE::Enabled,
482        }
483    }
484    ///Timestamp disabled
485    #[inline(always)]
486    pub fn is_disabled(&self) -> bool {
487        *self == TSE::Disabled
488    }
489    ///Timestamp enabled
490    #[inline(always)]
491    pub fn is_enabled(&self) -> bool {
492        *self == TSE::Enabled
493    }
494}
495///Field `TSE` writer - timestamp enable
496pub type TSE_W<'a, REG> = crate::BitWriter<'a, REG, TSE>;
497impl<'a, REG> TSE_W<'a, REG>
498where
499    REG: crate::Writable + crate::RegisterSpec,
500{
501    ///Timestamp disabled
502    #[inline(always)]
503    pub fn disabled(self) -> &'a mut crate::W<REG> {
504        self.variant(TSE::Disabled)
505    }
506    ///Timestamp enabled
507    #[inline(always)]
508    pub fn enabled(self) -> &'a mut crate::W<REG> {
509        self.variant(TSE::Enabled)
510    }
511}
512/**Alarm %s interrupt enable
513
514Value on reset: 0*/
515#[cfg_attr(feature = "defmt", derive(defmt::Format))]
516#[derive(Clone, Copy, Debug, PartialEq, Eq)]
517pub enum ALRAIE {
518    ///0: Alarm A interrupt disabled
519    Disabled = 0,
520    ///1: Alarm A interrupt enabled
521    Enabled = 1,
522}
523impl From<ALRAIE> for bool {
524    #[inline(always)]
525    fn from(variant: ALRAIE) -> Self {
526        variant as u8 != 0
527    }
528}
529///Field `ALRIE(A,B)` reader - Alarm %s interrupt enable
530pub type ALRIE_R = crate::BitReader<ALRAIE>;
531impl ALRIE_R {
532    ///Get enumerated values variant
533    #[inline(always)]
534    pub const fn variant(&self) -> ALRAIE {
535        match self.bits {
536            false => ALRAIE::Disabled,
537            true => ALRAIE::Enabled,
538        }
539    }
540    ///Alarm A interrupt disabled
541    #[inline(always)]
542    pub fn is_disabled(&self) -> bool {
543        *self == ALRAIE::Disabled
544    }
545    ///Alarm A interrupt enabled
546    #[inline(always)]
547    pub fn is_enabled(&self) -> bool {
548        *self == ALRAIE::Enabled
549    }
550}
551///Field `ALRIE(A,B)` writer - Alarm %s interrupt enable
552pub type ALRIE_W<'a, REG> = crate::BitWriter<'a, REG, ALRAIE>;
553impl<'a, REG> ALRIE_W<'a, REG>
554where
555    REG: crate::Writable + crate::RegisterSpec,
556{
557    ///Alarm A interrupt disabled
558    #[inline(always)]
559    pub fn disabled(self) -> &'a mut crate::W<REG> {
560        self.variant(ALRAIE::Disabled)
561    }
562    ///Alarm A interrupt enabled
563    #[inline(always)]
564    pub fn enabled(self) -> &'a mut crate::W<REG> {
565        self.variant(ALRAIE::Enabled)
566    }
567}
568/**Wakeup timer interrupt enable
569
570Value on reset: 0*/
571#[cfg_attr(feature = "defmt", derive(defmt::Format))]
572#[derive(Clone, Copy, Debug, PartialEq, Eq)]
573pub enum WUTIE {
574    ///0: Wakeup timer interrupt disabled
575    Disabled = 0,
576    ///1: Wakeup timer interrupt enabled
577    Enabled = 1,
578}
579impl From<WUTIE> for bool {
580    #[inline(always)]
581    fn from(variant: WUTIE) -> Self {
582        variant as u8 != 0
583    }
584}
585///Field `WUTIE` reader - Wakeup timer interrupt enable
586pub type WUTIE_R = crate::BitReader<WUTIE>;
587impl WUTIE_R {
588    ///Get enumerated values variant
589    #[inline(always)]
590    pub const fn variant(&self) -> WUTIE {
591        match self.bits {
592            false => WUTIE::Disabled,
593            true => WUTIE::Enabled,
594        }
595    }
596    ///Wakeup timer interrupt disabled
597    #[inline(always)]
598    pub fn is_disabled(&self) -> bool {
599        *self == WUTIE::Disabled
600    }
601    ///Wakeup timer interrupt enabled
602    #[inline(always)]
603    pub fn is_enabled(&self) -> bool {
604        *self == WUTIE::Enabled
605    }
606}
607///Field `WUTIE` writer - Wakeup timer interrupt enable
608pub type WUTIE_W<'a, REG> = crate::BitWriter<'a, REG, WUTIE>;
609impl<'a, REG> WUTIE_W<'a, REG>
610where
611    REG: crate::Writable + crate::RegisterSpec,
612{
613    ///Wakeup timer interrupt disabled
614    #[inline(always)]
615    pub fn disabled(self) -> &'a mut crate::W<REG> {
616        self.variant(WUTIE::Disabled)
617    }
618    ///Wakeup timer interrupt enabled
619    #[inline(always)]
620    pub fn enabled(self) -> &'a mut crate::W<REG> {
621        self.variant(WUTIE::Enabled)
622    }
623}
624/**Timestamp interrupt enable
625
626Value on reset: 0*/
627#[cfg_attr(feature = "defmt", derive(defmt::Format))]
628#[derive(Clone, Copy, Debug, PartialEq, Eq)]
629pub enum TSIE {
630    ///0: Time-stamp Interrupt disabled
631    Disabled = 0,
632    ///1: Time-stamp Interrupt enabled
633    Enabled = 1,
634}
635impl From<TSIE> for bool {
636    #[inline(always)]
637    fn from(variant: TSIE) -> Self {
638        variant as u8 != 0
639    }
640}
641///Field `TSIE` reader - Timestamp interrupt enable
642pub type TSIE_R = crate::BitReader<TSIE>;
643impl TSIE_R {
644    ///Get enumerated values variant
645    #[inline(always)]
646    pub const fn variant(&self) -> TSIE {
647        match self.bits {
648            false => TSIE::Disabled,
649            true => TSIE::Enabled,
650        }
651    }
652    ///Time-stamp Interrupt disabled
653    #[inline(always)]
654    pub fn is_disabled(&self) -> bool {
655        *self == TSIE::Disabled
656    }
657    ///Time-stamp Interrupt enabled
658    #[inline(always)]
659    pub fn is_enabled(&self) -> bool {
660        *self == TSIE::Enabled
661    }
662}
663///Field `TSIE` writer - Timestamp interrupt enable
664pub type TSIE_W<'a, REG> = crate::BitWriter<'a, REG, TSIE>;
665impl<'a, REG> TSIE_W<'a, REG>
666where
667    REG: crate::Writable + crate::RegisterSpec,
668{
669    ///Time-stamp Interrupt disabled
670    #[inline(always)]
671    pub fn disabled(self) -> &'a mut crate::W<REG> {
672        self.variant(TSIE::Disabled)
673    }
674    ///Time-stamp Interrupt enabled
675    #[inline(always)]
676    pub fn enabled(self) -> &'a mut crate::W<REG> {
677        self.variant(TSIE::Enabled)
678    }
679}
680/**Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.
681
682Value on reset: 0*/
683#[cfg_attr(feature = "defmt", derive(defmt::Format))]
684#[derive(Clone, Copy, Debug, PartialEq, Eq)]
685pub enum ADD1HW {
686    ///1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
687    Add1 = 1,
688}
689impl From<ADD1HW> for bool {
690    #[inline(always)]
691    fn from(variant: ADD1HW) -> Self {
692        variant as u8 != 0
693    }
694}
695///Field `ADD1H` writer - Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.
696pub type ADD1H_W<'a, REG> = crate::BitWriter<'a, REG, ADD1HW>;
697impl<'a, REG> ADD1H_W<'a, REG>
698where
699    REG: crate::Writable + crate::RegisterSpec,
700{
701    ///Adds 1 hour to the current time. This can be used for summer time change outside initialization mode
702    #[inline(always)]
703    pub fn add1(self) -> &'a mut crate::W<REG> {
704        self.variant(ADD1HW::Add1)
705    }
706}
707/**Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.
708
709Value on reset: 0*/
710#[cfg_attr(feature = "defmt", derive(defmt::Format))]
711#[derive(Clone, Copy, Debug, PartialEq, Eq)]
712pub enum SUB1HW {
713    ///1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
714    Sub1 = 1,
715}
716impl From<SUB1HW> for bool {
717    #[inline(always)]
718    fn from(variant: SUB1HW) -> Self {
719        variant as u8 != 0
720    }
721}
722///Field `SUB1H` writer - Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.
723pub type SUB1H_W<'a, REG> = crate::BitWriter<'a, REG, SUB1HW>;
724impl<'a, REG> SUB1H_W<'a, REG>
725where
726    REG: crate::Writable + crate::RegisterSpec,
727{
728    ///Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode
729    #[inline(always)]
730    pub fn sub1(self) -> &'a mut crate::W<REG> {
731        self.variant(SUB1HW::Sub1)
732    }
733}
734/**Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
735
736Value on reset: 0*/
737#[cfg_attr(feature = "defmt", derive(defmt::Format))]
738#[derive(Clone, Copy, Debug, PartialEq, Eq)]
739pub enum BKP {
740    ///0: Daylight Saving Time change has not been performed
741    DstnotChanged = 0,
742    ///1: Daylight Saving Time change has been performed
743    Dstchanged = 1,
744}
745impl From<BKP> for bool {
746    #[inline(always)]
747    fn from(variant: BKP) -> Self {
748        variant as u8 != 0
749    }
750}
751///Field `BKP` reader - Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
752pub type BKP_R = crate::BitReader<BKP>;
753impl BKP_R {
754    ///Get enumerated values variant
755    #[inline(always)]
756    pub const fn variant(&self) -> BKP {
757        match self.bits {
758            false => BKP::DstnotChanged,
759            true => BKP::Dstchanged,
760        }
761    }
762    ///Daylight Saving Time change has not been performed
763    #[inline(always)]
764    pub fn is_dstnot_changed(&self) -> bool {
765        *self == BKP::DstnotChanged
766    }
767    ///Daylight Saving Time change has been performed
768    #[inline(always)]
769    pub fn is_dstchanged(&self) -> bool {
770        *self == BKP::Dstchanged
771    }
772}
773///Field `BKP` writer - Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
774pub type BKP_W<'a, REG> = crate::BitWriter<'a, REG, BKP>;
775impl<'a, REG> BKP_W<'a, REG>
776where
777    REG: crate::Writable + crate::RegisterSpec,
778{
779    ///Daylight Saving Time change has not been performed
780    #[inline(always)]
781    pub fn dstnot_changed(self) -> &'a mut crate::W<REG> {
782        self.variant(BKP::DstnotChanged)
783    }
784    ///Daylight Saving Time change has been performed
785    #[inline(always)]
786    pub fn dstchanged(self) -> &'a mut crate::W<REG> {
787        self.variant(BKP::Dstchanged)
788    }
789}
790/**Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to .
791
792Value on reset: 0*/
793#[cfg_attr(feature = "defmt", derive(defmt::Format))]
794#[derive(Clone, Copy, Debug, PartialEq, Eq)]
795pub enum COSEL {
796    ///0: Calibration output is 512 Hz (with default prescaler setting)
797    CalFreq512hz = 0,
798    ///1: Calibration output is 1 Hz (with default prescaler setting)
799    CalFreq1hz = 1,
800}
801impl From<COSEL> for bool {
802    #[inline(always)]
803    fn from(variant: COSEL) -> Self {
804        variant as u8 != 0
805    }
806}
807///Field `COSEL` reader - Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to .
808pub type COSEL_R = crate::BitReader<COSEL>;
809impl COSEL_R {
810    ///Get enumerated values variant
811    #[inline(always)]
812    pub const fn variant(&self) -> COSEL {
813        match self.bits {
814            false => COSEL::CalFreq512hz,
815            true => COSEL::CalFreq1hz,
816        }
817    }
818    ///Calibration output is 512 Hz (with default prescaler setting)
819    #[inline(always)]
820    pub fn is_cal_freq_512hz(&self) -> bool {
821        *self == COSEL::CalFreq512hz
822    }
823    ///Calibration output is 1 Hz (with default prescaler setting)
824    #[inline(always)]
825    pub fn is_cal_freq_1hz(&self) -> bool {
826        *self == COSEL::CalFreq1hz
827    }
828}
829///Field `COSEL` writer - Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to .
830pub type COSEL_W<'a, REG> = crate::BitWriter<'a, REG, COSEL>;
831impl<'a, REG> COSEL_W<'a, REG>
832where
833    REG: crate::Writable + crate::RegisterSpec,
834{
835    ///Calibration output is 512 Hz (with default prescaler setting)
836    #[inline(always)]
837    pub fn cal_freq_512hz(self) -> &'a mut crate::W<REG> {
838        self.variant(COSEL::CalFreq512hz)
839    }
840    ///Calibration output is 1 Hz (with default prescaler setting)
841    #[inline(always)]
842    pub fn cal_freq_1hz(self) -> &'a mut crate::W<REG> {
843        self.variant(COSEL::CalFreq1hz)
844    }
845}
846/**Output polarity This bit is used to configure the polarity of TAMPALRM output.
847
848Value on reset: 0*/
849#[cfg_attr(feature = "defmt", derive(defmt::Format))]
850#[derive(Clone, Copy, Debug, PartialEq, Eq)]
851pub enum POL {
852    ///0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
853    High = 0,
854    ///1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
855    Low = 1,
856}
857impl From<POL> for bool {
858    #[inline(always)]
859    fn from(variant: POL) -> Self {
860        variant as u8 != 0
861    }
862}
863///Field `POL` reader - Output polarity This bit is used to configure the polarity of TAMPALRM output.
864pub type POL_R = crate::BitReader<POL>;
865impl POL_R {
866    ///Get enumerated values variant
867    #[inline(always)]
868    pub const fn variant(&self) -> POL {
869        match self.bits {
870            false => POL::High,
871            true => POL::Low,
872        }
873    }
874    ///The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
875    #[inline(always)]
876    pub fn is_high(&self) -> bool {
877        *self == POL::High
878    }
879    ///The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
880    #[inline(always)]
881    pub fn is_low(&self) -> bool {
882        *self == POL::Low
883    }
884}
885///Field `POL` writer - Output polarity This bit is used to configure the polarity of TAMPALRM output.
886pub type POL_W<'a, REG> = crate::BitWriter<'a, REG, POL>;
887impl<'a, REG> POL_W<'a, REG>
888where
889    REG: crate::Writable + crate::RegisterSpec,
890{
891    ///The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
892    #[inline(always)]
893    pub fn high(self) -> &'a mut crate::W<REG> {
894        self.variant(POL::High)
895    }
896    ///The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL\[1:0\])
897    #[inline(always)]
898    pub fn low(self) -> &'a mut crate::W<REG> {
899        self.variant(POL::Low)
900    }
901}
902/**Output selection These bits are used to select the flag to be routed to TAMPALRM output.
903
904Value on reset: 0*/
905#[cfg_attr(feature = "defmt", derive(defmt::Format))]
906#[derive(Clone, Copy, Debug, PartialEq, Eq)]
907#[repr(u8)]
908pub enum OSEL {
909    ///0: Output disabled
910    Disabled = 0,
911    ///1: Alarm A output enabled
912    AlarmA = 1,
913    ///2: Alarm B output enabled
914    AlarmB = 2,
915    ///3: Wakeup output enabled
916    Wakeup = 3,
917}
918impl From<OSEL> for u8 {
919    #[inline(always)]
920    fn from(variant: OSEL) -> Self {
921        variant as _
922    }
923}
924impl crate::FieldSpec for OSEL {
925    type Ux = u8;
926}
927impl crate::IsEnum for OSEL {}
928///Field `OSEL` reader - Output selection These bits are used to select the flag to be routed to TAMPALRM output.
929pub type OSEL_R = crate::FieldReader<OSEL>;
930impl OSEL_R {
931    ///Get enumerated values variant
932    #[inline(always)]
933    pub const fn variant(&self) -> OSEL {
934        match self.bits {
935            0 => OSEL::Disabled,
936            1 => OSEL::AlarmA,
937            2 => OSEL::AlarmB,
938            3 => OSEL::Wakeup,
939            _ => unreachable!(),
940        }
941    }
942    ///Output disabled
943    #[inline(always)]
944    pub fn is_disabled(&self) -> bool {
945        *self == OSEL::Disabled
946    }
947    ///Alarm A output enabled
948    #[inline(always)]
949    pub fn is_alarm_a(&self) -> bool {
950        *self == OSEL::AlarmA
951    }
952    ///Alarm B output enabled
953    #[inline(always)]
954    pub fn is_alarm_b(&self) -> bool {
955        *self == OSEL::AlarmB
956    }
957    ///Wakeup output enabled
958    #[inline(always)]
959    pub fn is_wakeup(&self) -> bool {
960        *self == OSEL::Wakeup
961    }
962}
963///Field `OSEL` writer - Output selection These bits are used to select the flag to be routed to TAMPALRM output.
964pub type OSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OSEL, crate::Safe>;
965impl<'a, REG> OSEL_W<'a, REG>
966where
967    REG: crate::Writable + crate::RegisterSpec,
968    REG::Ux: From<u8>,
969{
970    ///Output disabled
971    #[inline(always)]
972    pub fn disabled(self) -> &'a mut crate::W<REG> {
973        self.variant(OSEL::Disabled)
974    }
975    ///Alarm A output enabled
976    #[inline(always)]
977    pub fn alarm_a(self) -> &'a mut crate::W<REG> {
978        self.variant(OSEL::AlarmA)
979    }
980    ///Alarm B output enabled
981    #[inline(always)]
982    pub fn alarm_b(self) -> &'a mut crate::W<REG> {
983        self.variant(OSEL::AlarmB)
984    }
985    ///Wakeup output enabled
986    #[inline(always)]
987    pub fn wakeup(self) -> &'a mut crate::W<REG> {
988        self.variant(OSEL::Wakeup)
989    }
990}
991/**Calibration output enable This bit enables the CALIB output
992
993Value on reset: 0*/
994#[cfg_attr(feature = "defmt", derive(defmt::Format))]
995#[derive(Clone, Copy, Debug, PartialEq, Eq)]
996pub enum COE {
997    ///0: Calibration output disabled
998    Disabled = 0,
999    ///1: Calibration output enabled
1000    Enabled = 1,
1001}
1002impl From<COE> for bool {
1003    #[inline(always)]
1004    fn from(variant: COE) -> Self {
1005        variant as u8 != 0
1006    }
1007}
1008///Field `COE` reader - Calibration output enable This bit enables the CALIB output
1009pub type COE_R = crate::BitReader<COE>;
1010impl COE_R {
1011    ///Get enumerated values variant
1012    #[inline(always)]
1013    pub const fn variant(&self) -> COE {
1014        match self.bits {
1015            false => COE::Disabled,
1016            true => COE::Enabled,
1017        }
1018    }
1019    ///Calibration output disabled
1020    #[inline(always)]
1021    pub fn is_disabled(&self) -> bool {
1022        *self == COE::Disabled
1023    }
1024    ///Calibration output enabled
1025    #[inline(always)]
1026    pub fn is_enabled(&self) -> bool {
1027        *self == COE::Enabled
1028    }
1029}
1030///Field `COE` writer - Calibration output enable This bit enables the CALIB output
1031pub type COE_W<'a, REG> = crate::BitWriter<'a, REG, COE>;
1032impl<'a, REG> COE_W<'a, REG>
1033where
1034    REG: crate::Writable + crate::RegisterSpec,
1035{
1036    ///Calibration output disabled
1037    #[inline(always)]
1038    pub fn disabled(self) -> &'a mut crate::W<REG> {
1039        self.variant(COE::Disabled)
1040    }
1041    ///Calibration output enabled
1042    #[inline(always)]
1043    pub fn enabled(self) -> &'a mut crate::W<REG> {
1044        self.variant(COE::Enabled)
1045    }
1046}
1047/**timestamp on internal event enable
1048
1049Value on reset: 0*/
1050#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1051#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1052pub enum ITSE {
1053    ///0: Internal event timestamp disabled
1054    Disabled = 0,
1055    ///1: Internal event timestamp enabled
1056    Enabled = 1,
1057}
1058impl From<ITSE> for bool {
1059    #[inline(always)]
1060    fn from(variant: ITSE) -> Self {
1061        variant as u8 != 0
1062    }
1063}
1064///Field `ITSE` reader - timestamp on internal event enable
1065pub type ITSE_R = crate::BitReader<ITSE>;
1066impl ITSE_R {
1067    ///Get enumerated values variant
1068    #[inline(always)]
1069    pub const fn variant(&self) -> ITSE {
1070        match self.bits {
1071            false => ITSE::Disabled,
1072            true => ITSE::Enabled,
1073        }
1074    }
1075    ///Internal event timestamp disabled
1076    #[inline(always)]
1077    pub fn is_disabled(&self) -> bool {
1078        *self == ITSE::Disabled
1079    }
1080    ///Internal event timestamp enabled
1081    #[inline(always)]
1082    pub fn is_enabled(&self) -> bool {
1083        *self == ITSE::Enabled
1084    }
1085}
1086///Field `ITSE` writer - timestamp on internal event enable
1087pub type ITSE_W<'a, REG> = crate::BitWriter<'a, REG, ITSE>;
1088impl<'a, REG> ITSE_W<'a, REG>
1089where
1090    REG: crate::Writable + crate::RegisterSpec,
1091{
1092    ///Internal event timestamp disabled
1093    #[inline(always)]
1094    pub fn disabled(self) -> &'a mut crate::W<REG> {
1095        self.variant(ITSE::Disabled)
1096    }
1097    ///Internal event timestamp enabled
1098    #[inline(always)]
1099    pub fn enabled(self) -> &'a mut crate::W<REG> {
1100        self.variant(ITSE::Enabled)
1101    }
1102}
1103/**Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts.
1104
1105Value on reset: 0*/
1106#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1107#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1108pub enum TAMPTS {
1109    ///0: Tamper detection event does not cause a RTC timestamp to be saved
1110    Disabled = 0,
1111    ///1: Save RTC timestamp on tamper detection event
1112    Enabled = 1,
1113}
1114impl From<TAMPTS> for bool {
1115    #[inline(always)]
1116    fn from(variant: TAMPTS) -> Self {
1117        variant as u8 != 0
1118    }
1119}
1120///Field `TAMPTS` reader - Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts.
1121pub type TAMPTS_R = crate::BitReader<TAMPTS>;
1122impl TAMPTS_R {
1123    ///Get enumerated values variant
1124    #[inline(always)]
1125    pub const fn variant(&self) -> TAMPTS {
1126        match self.bits {
1127            false => TAMPTS::Disabled,
1128            true => TAMPTS::Enabled,
1129        }
1130    }
1131    ///Tamper detection event does not cause a RTC timestamp to be saved
1132    #[inline(always)]
1133    pub fn is_disabled(&self) -> bool {
1134        *self == TAMPTS::Disabled
1135    }
1136    ///Save RTC timestamp on tamper detection event
1137    #[inline(always)]
1138    pub fn is_enabled(&self) -> bool {
1139        *self == TAMPTS::Enabled
1140    }
1141}
1142///Field `TAMPTS` writer - Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts.
1143pub type TAMPTS_W<'a, REG> = crate::BitWriter<'a, REG, TAMPTS>;
1144impl<'a, REG> TAMPTS_W<'a, REG>
1145where
1146    REG: crate::Writable + crate::RegisterSpec,
1147{
1148    ///Tamper detection event does not cause a RTC timestamp to be saved
1149    #[inline(always)]
1150    pub fn disabled(self) -> &'a mut crate::W<REG> {
1151        self.variant(TAMPTS::Disabled)
1152    }
1153    ///Save RTC timestamp on tamper detection event
1154    #[inline(always)]
1155    pub fn enabled(self) -> &'a mut crate::W<REG> {
1156        self.variant(TAMPTS::Enabled)
1157    }
1158}
1159/**Tamper detection output enable on TAMPALRM
1160
1161Value on reset: 0*/
1162#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1163#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1164pub enum TAMPOE {
1165    ///0: The tamper flag is not routed on TAMPALRM
1166    Disabled = 0,
1167    ///1: The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL
1168    Enabled = 1,
1169}
1170impl From<TAMPOE> for bool {
1171    #[inline(always)]
1172    fn from(variant: TAMPOE) -> Self {
1173        variant as u8 != 0
1174    }
1175}
1176///Field `TAMPOE` reader - Tamper detection output enable on TAMPALRM
1177pub type TAMPOE_R = crate::BitReader<TAMPOE>;
1178impl TAMPOE_R {
1179    ///Get enumerated values variant
1180    #[inline(always)]
1181    pub const fn variant(&self) -> TAMPOE {
1182        match self.bits {
1183            false => TAMPOE::Disabled,
1184            true => TAMPOE::Enabled,
1185        }
1186    }
1187    ///The tamper flag is not routed on TAMPALRM
1188    #[inline(always)]
1189    pub fn is_disabled(&self) -> bool {
1190        *self == TAMPOE::Disabled
1191    }
1192    ///The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL
1193    #[inline(always)]
1194    pub fn is_enabled(&self) -> bool {
1195        *self == TAMPOE::Enabled
1196    }
1197}
1198///Field `TAMPOE` writer - Tamper detection output enable on TAMPALRM
1199pub type TAMPOE_W<'a, REG> = crate::BitWriter<'a, REG, TAMPOE>;
1200impl<'a, REG> TAMPOE_W<'a, REG>
1201where
1202    REG: crate::Writable + crate::RegisterSpec,
1203{
1204    ///The tamper flag is not routed on TAMPALRM
1205    #[inline(always)]
1206    pub fn disabled(self) -> &'a mut crate::W<REG> {
1207        self.variant(TAMPOE::Disabled)
1208    }
1209    ///The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL
1210    #[inline(always)]
1211    pub fn enabled(self) -> &'a mut crate::W<REG> {
1212        self.variant(TAMPOE::Enabled)
1213    }
1214}
1215/**TAMPALRM pull-up enable
1216
1217Value on reset: 0*/
1218#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1219#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1220pub enum TAMPALRM_PU {
1221    ///0: No pull-up is applied on TAMPALRM output
1222    NoPullUp = 0,
1223    ///1: A pull-up is applied on TAMPALRM output
1224    PullUp = 1,
1225}
1226impl From<TAMPALRM_PU> for bool {
1227    #[inline(always)]
1228    fn from(variant: TAMPALRM_PU) -> Self {
1229        variant as u8 != 0
1230    }
1231}
1232///Field `TAMPALRM_PU` reader - TAMPALRM pull-up enable
1233pub type TAMPALRM_PU_R = crate::BitReader<TAMPALRM_PU>;
1234impl TAMPALRM_PU_R {
1235    ///Get enumerated values variant
1236    #[inline(always)]
1237    pub const fn variant(&self) -> TAMPALRM_PU {
1238        match self.bits {
1239            false => TAMPALRM_PU::NoPullUp,
1240            true => TAMPALRM_PU::PullUp,
1241        }
1242    }
1243    ///No pull-up is applied on TAMPALRM output
1244    #[inline(always)]
1245    pub fn is_no_pull_up(&self) -> bool {
1246        *self == TAMPALRM_PU::NoPullUp
1247    }
1248    ///A pull-up is applied on TAMPALRM output
1249    #[inline(always)]
1250    pub fn is_pull_up(&self) -> bool {
1251        *self == TAMPALRM_PU::PullUp
1252    }
1253}
1254///Field `TAMPALRM_PU` writer - TAMPALRM pull-up enable
1255pub type TAMPALRM_PU_W<'a, REG> = crate::BitWriter<'a, REG, TAMPALRM_PU>;
1256impl<'a, REG> TAMPALRM_PU_W<'a, REG>
1257where
1258    REG: crate::Writable + crate::RegisterSpec,
1259{
1260    ///No pull-up is applied on TAMPALRM output
1261    #[inline(always)]
1262    pub fn no_pull_up(self) -> &'a mut crate::W<REG> {
1263        self.variant(TAMPALRM_PU::NoPullUp)
1264    }
1265    ///A pull-up is applied on TAMPALRM output
1266    #[inline(always)]
1267    pub fn pull_up(self) -> &'a mut crate::W<REG> {
1268        self.variant(TAMPALRM_PU::PullUp)
1269    }
1270}
1271/**TAMPALRM output type
1272
1273Value on reset: 0*/
1274#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1275#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1276pub enum TAMPALRM_TYPE {
1277    ///0: TAMPALRM is push-pull output
1278    PushPull = 0,
1279    ///1: TAMPALRM is open-drain output
1280    OpenDrain = 1,
1281}
1282impl From<TAMPALRM_TYPE> for bool {
1283    #[inline(always)]
1284    fn from(variant: TAMPALRM_TYPE) -> Self {
1285        variant as u8 != 0
1286    }
1287}
1288///Field `TAMPALRM_TYPE` reader - TAMPALRM output type
1289pub type TAMPALRM_TYPE_R = crate::BitReader<TAMPALRM_TYPE>;
1290impl TAMPALRM_TYPE_R {
1291    ///Get enumerated values variant
1292    #[inline(always)]
1293    pub const fn variant(&self) -> TAMPALRM_TYPE {
1294        match self.bits {
1295            false => TAMPALRM_TYPE::PushPull,
1296            true => TAMPALRM_TYPE::OpenDrain,
1297        }
1298    }
1299    ///TAMPALRM is push-pull output
1300    #[inline(always)]
1301    pub fn is_push_pull(&self) -> bool {
1302        *self == TAMPALRM_TYPE::PushPull
1303    }
1304    ///TAMPALRM is open-drain output
1305    #[inline(always)]
1306    pub fn is_open_drain(&self) -> bool {
1307        *self == TAMPALRM_TYPE::OpenDrain
1308    }
1309}
1310///Field `TAMPALRM_TYPE` writer - TAMPALRM output type
1311pub type TAMPALRM_TYPE_W<'a, REG> = crate::BitWriter<'a, REG, TAMPALRM_TYPE>;
1312impl<'a, REG> TAMPALRM_TYPE_W<'a, REG>
1313where
1314    REG: crate::Writable + crate::RegisterSpec,
1315{
1316    ///TAMPALRM is push-pull output
1317    #[inline(always)]
1318    pub fn push_pull(self) -> &'a mut crate::W<REG> {
1319        self.variant(TAMPALRM_TYPE::PushPull)
1320    }
1321    ///TAMPALRM is open-drain output
1322    #[inline(always)]
1323    pub fn open_drain(self) -> &'a mut crate::W<REG> {
1324        self.variant(TAMPALRM_TYPE::OpenDrain)
1325    }
1326}
1327/**RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL different 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1.
1328
1329Value on reset: 0*/
1330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1332pub enum OUT2EN {
1333    ///0: RTC output 2 disable
1334    Disabled = 0,
1335    ///1: RTC output 2 enable
1336    Enabled = 1,
1337}
1338impl From<OUT2EN> for bool {
1339    #[inline(always)]
1340    fn from(variant: OUT2EN) -> Self {
1341        variant as u8 != 0
1342    }
1343}
1344///Field `OUT2EN` reader - RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL different 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1.
1345pub type OUT2EN_R = crate::BitReader<OUT2EN>;
1346impl OUT2EN_R {
1347    ///Get enumerated values variant
1348    #[inline(always)]
1349    pub const fn variant(&self) -> OUT2EN {
1350        match self.bits {
1351            false => OUT2EN::Disabled,
1352            true => OUT2EN::Enabled,
1353        }
1354    }
1355    ///RTC output 2 disable
1356    #[inline(always)]
1357    pub fn is_disabled(&self) -> bool {
1358        *self == OUT2EN::Disabled
1359    }
1360    ///RTC output 2 enable
1361    #[inline(always)]
1362    pub fn is_enabled(&self) -> bool {
1363        *self == OUT2EN::Enabled
1364    }
1365}
1366///Field `OUT2EN` writer - RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL different 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1.
1367pub type OUT2EN_W<'a, REG> = crate::BitWriter<'a, REG, OUT2EN>;
1368impl<'a, REG> OUT2EN_W<'a, REG>
1369where
1370    REG: crate::Writable + crate::RegisterSpec,
1371{
1372    ///RTC output 2 disable
1373    #[inline(always)]
1374    pub fn disabled(self) -> &'a mut crate::W<REG> {
1375        self.variant(OUT2EN::Disabled)
1376    }
1377    ///RTC output 2 enable
1378    #[inline(always)]
1379    pub fn enabled(self) -> &'a mut crate::W<REG> {
1380        self.variant(OUT2EN::Enabled)
1381    }
1382}
1383impl R {
1384    ///Bits 0:2 - ck_wut wakeup clock selection 10x: ck_spre (usually 1Hz) clock is selected 11x: ck_spre (usually 1Hz) clock is selected and 216is added to the WUT counter value
1385    #[inline(always)]
1386    pub fn wucksel(&self) -> WUCKSEL_R {
1387        WUCKSEL_R::new((self.bits & 7) as u8)
1388    }
1389    ///Bit 3 - Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
1390    #[inline(always)]
1391    pub fn tsedge(&self) -> TSEDGE_R {
1392        TSEDGE_R::new(((self.bits >> 3) & 1) != 0)
1393    }
1394    ///Bit 4 - RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF.
1395    #[inline(always)]
1396    pub fn refckon(&self) -> REFCKON_R {
1397        REFCKON_R::new(((self.bits >> 4) & 1) != 0)
1398    }
1399    ///Bit 5 - Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
1400    #[inline(always)]
1401    pub fn bypshad(&self) -> BYPSHAD_R {
1402        BYPSHAD_R::new(((self.bits >> 5) & 1) != 0)
1403    }
1404    ///Bit 6 - Hour format
1405    #[inline(always)]
1406    pub fn fmt(&self) -> FMT_R {
1407        FMT_R::new(((self.bits >> 6) & 1) != 0)
1408    }
1409    ///Alarm (A,B) enable
1410    ///
1411    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAE` field.</div>
1412    #[inline(always)]
1413    pub fn alre(&self, n: u8) -> ALRE_R {
1414        #[allow(clippy::no_effect)] [(); 2][n as usize];
1415        ALRE_R::new(((self.bits >> (n + 8)) & 1) != 0)
1416    }
1417    ///Iterator for array of:
1418    ///Alarm (A,B) enable
1419    #[inline(always)]
1420    pub fn alre_iter(&self) -> impl Iterator<Item = ALRE_R> + '_ {
1421        (0..2).map(move |n| ALRE_R::new(((self.bits >> (n + 8)) & 1) != 0))
1422    }
1423    ///Bit 8 - Alarm A enable
1424    #[inline(always)]
1425    pub fn alrae(&self) -> ALRE_R {
1426        ALRE_R::new(((self.bits >> 8) & 1) != 0)
1427    }
1428    ///Bit 9 - Alarm B enable
1429    #[inline(always)]
1430    pub fn alrbe(&self) -> ALRE_R {
1431        ALRE_R::new(((self.bits >> 9) & 1) != 0)
1432    }
1433    ///Bit 10 - Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
1434    #[inline(always)]
1435    pub fn wute(&self) -> WUTE_R {
1436        WUTE_R::new(((self.bits >> 10) & 1) != 0)
1437    }
1438    ///Bit 11 - timestamp enable
1439    #[inline(always)]
1440    pub fn tse(&self) -> TSE_R {
1441        TSE_R::new(((self.bits >> 11) & 1) != 0)
1442    }
1443    ///Alarm (A,B) interrupt enable
1444    ///
1445    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAIE` field.</div>
1446    #[inline(always)]
1447    pub fn alrie(&self, n: u8) -> ALRIE_R {
1448        #[allow(clippy::no_effect)] [(); 2][n as usize];
1449        ALRIE_R::new(((self.bits >> (n + 12)) & 1) != 0)
1450    }
1451    ///Iterator for array of:
1452    ///Alarm (A,B) interrupt enable
1453    #[inline(always)]
1454    pub fn alrie_iter(&self) -> impl Iterator<Item = ALRIE_R> + '_ {
1455        (0..2).map(move |n| ALRIE_R::new(((self.bits >> (n + 12)) & 1) != 0))
1456    }
1457    ///Bit 12 - Alarm A interrupt enable
1458    #[inline(always)]
1459    pub fn alraie(&self) -> ALRIE_R {
1460        ALRIE_R::new(((self.bits >> 12) & 1) != 0)
1461    }
1462    ///Bit 13 - Alarm B interrupt enable
1463    #[inline(always)]
1464    pub fn alrbie(&self) -> ALRIE_R {
1465        ALRIE_R::new(((self.bits >> 13) & 1) != 0)
1466    }
1467    ///Bit 14 - Wakeup timer interrupt enable
1468    #[inline(always)]
1469    pub fn wutie(&self) -> WUTIE_R {
1470        WUTIE_R::new(((self.bits >> 14) & 1) != 0)
1471    }
1472    ///Bit 15 - Timestamp interrupt enable
1473    #[inline(always)]
1474    pub fn tsie(&self) -> TSIE_R {
1475        TSIE_R::new(((self.bits >> 15) & 1) != 0)
1476    }
1477    ///Bit 18 - Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
1478    #[inline(always)]
1479    pub fn bkp(&self) -> BKP_R {
1480        BKP_R::new(((self.bits >> 18) & 1) != 0)
1481    }
1482    ///Bit 19 - Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to .
1483    #[inline(always)]
1484    pub fn cosel(&self) -> COSEL_R {
1485        COSEL_R::new(((self.bits >> 19) & 1) != 0)
1486    }
1487    ///Bit 20 - Output polarity This bit is used to configure the polarity of TAMPALRM output.
1488    #[inline(always)]
1489    pub fn pol(&self) -> POL_R {
1490        POL_R::new(((self.bits >> 20) & 1) != 0)
1491    }
1492    ///Bits 21:22 - Output selection These bits are used to select the flag to be routed to TAMPALRM output.
1493    #[inline(always)]
1494    pub fn osel(&self) -> OSEL_R {
1495        OSEL_R::new(((self.bits >> 21) & 3) as u8)
1496    }
1497    ///Bit 23 - Calibration output enable This bit enables the CALIB output
1498    #[inline(always)]
1499    pub fn coe(&self) -> COE_R {
1500        COE_R::new(((self.bits >> 23) & 1) != 0)
1501    }
1502    ///Bit 24 - timestamp on internal event enable
1503    #[inline(always)]
1504    pub fn itse(&self) -> ITSE_R {
1505        ITSE_R::new(((self.bits >> 24) & 1) != 0)
1506    }
1507    ///Bit 25 - Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts.
1508    #[inline(always)]
1509    pub fn tampts(&self) -> TAMPTS_R {
1510        TAMPTS_R::new(((self.bits >> 25) & 1) != 0)
1511    }
1512    ///Bit 26 - Tamper detection output enable on TAMPALRM
1513    #[inline(always)]
1514    pub fn tampoe(&self) -> TAMPOE_R {
1515        TAMPOE_R::new(((self.bits >> 26) & 1) != 0)
1516    }
1517    ///Bit 29 - TAMPALRM pull-up enable
1518    #[inline(always)]
1519    pub fn tampalrm_pu(&self) -> TAMPALRM_PU_R {
1520        TAMPALRM_PU_R::new(((self.bits >> 29) & 1) != 0)
1521    }
1522    ///Bit 30 - TAMPALRM output type
1523    #[inline(always)]
1524    pub fn tampalrm_type(&self) -> TAMPALRM_TYPE_R {
1525        TAMPALRM_TYPE_R::new(((self.bits >> 30) & 1) != 0)
1526    }
1527    ///Bit 31 - RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL different 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1.
1528    #[inline(always)]
1529    pub fn out2en(&self) -> OUT2EN_R {
1530        OUT2EN_R::new(((self.bits >> 31) & 1) != 0)
1531    }
1532}
1533impl core::fmt::Debug for R {
1534    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1535        f.debug_struct("CR")
1536            .field("wucksel", &self.wucksel())
1537            .field("tsedge", &self.tsedge())
1538            .field("refckon", &self.refckon())
1539            .field("bypshad", &self.bypshad())
1540            .field("fmt", &self.fmt())
1541            .field("alrae", &self.alrae())
1542            .field("alrbe", &self.alrbe())
1543            .field("wute", &self.wute())
1544            .field("tse", &self.tse())
1545            .field("alraie", &self.alraie())
1546            .field("alrbie", &self.alrbie())
1547            .field("wutie", &self.wutie())
1548            .field("tsie", &self.tsie())
1549            .field("bkp", &self.bkp())
1550            .field("cosel", &self.cosel())
1551            .field("pol", &self.pol())
1552            .field("osel", &self.osel())
1553            .field("coe", &self.coe())
1554            .field("itse", &self.itse())
1555            .field("tampts", &self.tampts())
1556            .field("tampoe", &self.tampoe())
1557            .field("tampalrm_pu", &self.tampalrm_pu())
1558            .field("tampalrm_type", &self.tampalrm_type())
1559            .field("out2en", &self.out2en())
1560            .finish()
1561    }
1562}
1563impl W {
1564    ///Bits 0:2 - ck_wut wakeup clock selection 10x: ck_spre (usually 1Hz) clock is selected 11x: ck_spre (usually 1Hz) clock is selected and 216is added to the WUT counter value
1565    #[inline(always)]
1566    pub fn wucksel(&mut self) -> WUCKSEL_W<CRrs> {
1567        WUCKSEL_W::new(self, 0)
1568    }
1569    ///Bit 3 - Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
1570    #[inline(always)]
1571    pub fn tsedge(&mut self) -> TSEDGE_W<CRrs> {
1572        TSEDGE_W::new(self, 3)
1573    }
1574    ///Bit 4 - RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF.
1575    #[inline(always)]
1576    pub fn refckon(&mut self) -> REFCKON_W<CRrs> {
1577        REFCKON_W::new(self, 4)
1578    }
1579    ///Bit 5 - Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
1580    #[inline(always)]
1581    pub fn bypshad(&mut self) -> BYPSHAD_W<CRrs> {
1582        BYPSHAD_W::new(self, 5)
1583    }
1584    ///Bit 6 - Hour format
1585    #[inline(always)]
1586    pub fn fmt(&mut self) -> FMT_W<CRrs> {
1587        FMT_W::new(self, 6)
1588    }
1589    ///Alarm (A,B) enable
1590    ///
1591    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAE` field.</div>
1592    #[inline(always)]
1593    pub fn alre(&mut self, n: u8) -> ALRE_W<CRrs> {
1594        #[allow(clippy::no_effect)] [(); 2][n as usize];
1595        ALRE_W::new(self, n + 8)
1596    }
1597    ///Bit 8 - Alarm A enable
1598    #[inline(always)]
1599    pub fn alrae(&mut self) -> ALRE_W<CRrs> {
1600        ALRE_W::new(self, 8)
1601    }
1602    ///Bit 9 - Alarm B enable
1603    #[inline(always)]
1604    pub fn alrbe(&mut self) -> ALRE_W<CRrs> {
1605        ALRE_W::new(self, 9)
1606    }
1607    ///Bit 10 - Wakeup timer enable Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
1608    #[inline(always)]
1609    pub fn wute(&mut self) -> WUTE_W<CRrs> {
1610        WUTE_W::new(self, 10)
1611    }
1612    ///Bit 11 - timestamp enable
1613    #[inline(always)]
1614    pub fn tse(&mut self) -> TSE_W<CRrs> {
1615        TSE_W::new(self, 11)
1616    }
1617    ///Alarm (A,B) interrupt enable
1618    ///
1619    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAIE` field.</div>
1620    #[inline(always)]
1621    pub fn alrie(&mut self, n: u8) -> ALRIE_W<CRrs> {
1622        #[allow(clippy::no_effect)] [(); 2][n as usize];
1623        ALRIE_W::new(self, n + 12)
1624    }
1625    ///Bit 12 - Alarm A interrupt enable
1626    #[inline(always)]
1627    pub fn alraie(&mut self) -> ALRIE_W<CRrs> {
1628        ALRIE_W::new(self, 12)
1629    }
1630    ///Bit 13 - Alarm B interrupt enable
1631    #[inline(always)]
1632    pub fn alrbie(&mut self) -> ALRIE_W<CRrs> {
1633        ALRIE_W::new(self, 13)
1634    }
1635    ///Bit 14 - Wakeup timer interrupt enable
1636    #[inline(always)]
1637    pub fn wutie(&mut self) -> WUTIE_W<CRrs> {
1638        WUTIE_W::new(self, 14)
1639    }
1640    ///Bit 15 - Timestamp interrupt enable
1641    #[inline(always)]
1642    pub fn tsie(&mut self) -> TSIE_W<CRrs> {
1643        TSIE_W::new(self, 15)
1644    }
1645    ///Bit 16 - Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.
1646    #[inline(always)]
1647    pub fn add1h(&mut self) -> ADD1H_W<CRrs> {
1648        ADD1H_W::new(self, 16)
1649    }
1650    ///Bit 17 - Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.
1651    #[inline(always)]
1652    pub fn sub1h(&mut self) -> SUB1H_W<CRrs> {
1653        SUB1H_W::new(self, 17)
1654    }
1655    ///Bit 18 - Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
1656    #[inline(always)]
1657    pub fn bkp(&mut self) -> BKP_W<CRrs> {
1658        BKP_W::new(self, 18)
1659    }
1660    ///Bit 19 - Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to .
1661    #[inline(always)]
1662    pub fn cosel(&mut self) -> COSEL_W<CRrs> {
1663        COSEL_W::new(self, 19)
1664    }
1665    ///Bit 20 - Output polarity This bit is used to configure the polarity of TAMPALRM output.
1666    #[inline(always)]
1667    pub fn pol(&mut self) -> POL_W<CRrs> {
1668        POL_W::new(self, 20)
1669    }
1670    ///Bits 21:22 - Output selection These bits are used to select the flag to be routed to TAMPALRM output.
1671    #[inline(always)]
1672    pub fn osel(&mut self) -> OSEL_W<CRrs> {
1673        OSEL_W::new(self, 21)
1674    }
1675    ///Bit 23 - Calibration output enable This bit enables the CALIB output
1676    #[inline(always)]
1677    pub fn coe(&mut self) -> COE_W<CRrs> {
1678        COE_W::new(self, 23)
1679    }
1680    ///Bit 24 - timestamp on internal event enable
1681    #[inline(always)]
1682    pub fn itse(&mut self) -> ITSE_W<CRrs> {
1683        ITSE_W::new(self, 24)
1684    }
1685    ///Bit 25 - Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts.
1686    #[inline(always)]
1687    pub fn tampts(&mut self) -> TAMPTS_W<CRrs> {
1688        TAMPTS_W::new(self, 25)
1689    }
1690    ///Bit 26 - Tamper detection output enable on TAMPALRM
1691    #[inline(always)]
1692    pub fn tampoe(&mut self) -> TAMPOE_W<CRrs> {
1693        TAMPOE_W::new(self, 26)
1694    }
1695    ///Bit 29 - TAMPALRM pull-up enable
1696    #[inline(always)]
1697    pub fn tampalrm_pu(&mut self) -> TAMPALRM_PU_W<CRrs> {
1698        TAMPALRM_PU_W::new(self, 29)
1699    }
1700    ///Bit 30 - TAMPALRM output type
1701    #[inline(always)]
1702    pub fn tampalrm_type(&mut self) -> TAMPALRM_TYPE_W<CRrs> {
1703        TAMPALRM_TYPE_W::new(self, 30)
1704    }
1705    ///Bit 31 - RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL different 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL different 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSEL different 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1.
1706    #[inline(always)]
1707    pub fn out2en(&mut self) -> OUT2EN_W<CRrs> {
1708        OUT2EN_W::new(self, 31)
1709    }
1710}
1711/**control register
1712
1713You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
1714
1715See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RTC:CR)*/
1716pub struct CRrs;
1717impl crate::RegisterSpec for CRrs {
1718    type Ux = u32;
1719}
1720///`read()` method returns [`cr::R`](R) reader structure
1721impl crate::Readable for CRrs {}
1722///`write(|w| ..)` method takes [`cr::W`](W) writer structure
1723impl crate::Writable for CRrs {
1724    type Safety = crate::Unsafe;
1725    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1726    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1727}
1728///`reset()` method sets CR to value 0
1729impl crate::Resettable for CRrs {
1730    const RESET_VALUE: u32 = 0;
1731}
stm32g0_staging/stm32g0b0/rtc/cr.rs

stm32g0_staging/stm32g0b0/rtc/
cr.rs
