stm32g0_staging/stm32g0b0/
i2c1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    oar1: OAR1,
8    oar2: OAR2,
9    timingr: TIMINGR,
10    timeoutr: TIMEOUTR,
11    isr: ISR,
12    icr: ICR,
13    pecr: PECR,
14    rxdr: RXDR,
15    txdr: TXDR,
16}
17impl RegisterBlock {
18    ///0x00 - Control register 1
19    #[inline(always)]
20    pub const fn cr1(&self) -> &CR1 {
21        &self.cr1
22    }
23    ///0x04 - Control register 2
24    #[inline(always)]
25    pub const fn cr2(&self) -> &CR2 {
26        &self.cr2
27    }
28    ///0x08 - Own address register 1
29    #[inline(always)]
30    pub const fn oar1(&self) -> &OAR1 {
31        &self.oar1
32    }
33    ///0x0c - Own address register 2
34    #[inline(always)]
35    pub const fn oar2(&self) -> &OAR2 {
36        &self.oar2
37    }
38    ///0x10 - Timing register
39    #[inline(always)]
40    pub const fn timingr(&self) -> &TIMINGR {
41        &self.timingr
42    }
43    ///0x14 - Status register 1
44    #[inline(always)]
45    pub const fn timeoutr(&self) -> &TIMEOUTR {
46        &self.timeoutr
47    }
48    ///0x18 - Interrupt and Status register
49    #[inline(always)]
50    pub const fn isr(&self) -> &ISR {
51        &self.isr
52    }
53    ///0x1c - Interrupt clear register
54    #[inline(always)]
55    pub const fn icr(&self) -> &ICR {
56        &self.icr
57    }
58    ///0x20 - PEC register
59    #[inline(always)]
60    pub const fn pecr(&self) -> &PECR {
61        &self.pecr
62    }
63    ///0x24 - Receive data register
64    #[inline(always)]
65    pub const fn rxdr(&self) -> &RXDR {
66        &self.rxdr
67    }
68    ///0x28 - Transmit data register
69    #[inline(always)]
70    pub const fn txdr(&self) -> &TXDR {
71        &self.txdr
72    }
73}
74/**CR1 (rw) register accessor: Control register 1
75
76You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
77
78See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:CR1)
79
80For information about available fields see [`mod@cr1`]
81module*/
82pub type CR1 = crate::Reg<cr1::CR1rs>;
83///Control register 1
84pub mod cr1;
85/**CR2 (rw) register accessor: Control register 2
86
87You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
88
89See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:CR2)
90
91For information about available fields see [`mod@cr2`]
92module*/
93pub type CR2 = crate::Reg<cr2::CR2rs>;
94///Control register 2
95pub mod cr2;
96/**OAR1 (rw) register accessor: Own address register 1
97
98You can [`read`](crate::Reg::read) this register and get [`oar1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oar1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
99
100See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:OAR1)
101
102For information about available fields see [`mod@oar1`]
103module*/
104pub type OAR1 = crate::Reg<oar1::OAR1rs>;
105///Own address register 1
106pub mod oar1;
107/**OAR2 (rw) register accessor: Own address register 2
108
109You can [`read`](crate::Reg::read) this register and get [`oar2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oar2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
110
111See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:OAR2)
112
113For information about available fields see [`mod@oar2`]
114module*/
115pub type OAR2 = crate::Reg<oar2::OAR2rs>;
116///Own address register 2
117pub mod oar2;
118/**TIMINGR (rw) register accessor: Timing register
119
120You can [`read`](crate::Reg::read) this register and get [`timingr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timingr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
121
122See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:TIMINGR)
123
124For information about available fields see [`mod@timingr`]
125module*/
126pub type TIMINGR = crate::Reg<timingr::TIMINGRrs>;
127///Timing register
128pub mod timingr;
129/**TIMEOUTR (rw) register accessor: Status register 1
130
131You can [`read`](crate::Reg::read) this register and get [`timeoutr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timeoutr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
132
133See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:TIMEOUTR)
134
135For information about available fields see [`mod@timeoutr`]
136module*/
137pub type TIMEOUTR = crate::Reg<timeoutr::TIMEOUTRrs>;
138///Status register 1
139pub mod timeoutr;
140/**ISR (rw) register accessor: Interrupt and Status register
141
142You can [`read`](crate::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:ISR)
145
146For information about available fields see [`mod@isr`]
147module*/
148pub type ISR = crate::Reg<isr::ISRrs>;
149///Interrupt and Status register
150pub mod isr;
151/**ICR (w) register accessor: Interrupt clear register
152
153You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
154
155See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:ICR)
156
157For information about available fields see [`mod@icr`]
158module*/
159pub type ICR = crate::Reg<icr::ICRrs>;
160///Interrupt clear register
161pub mod icr;
162/**PECR (r) register accessor: PEC register
163
164You can [`read`](crate::Reg::read) this register and get [`pecr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
165
166See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:PECR)
167
168For information about available fields see [`mod@pecr`]
169module*/
170pub type PECR = crate::Reg<pecr::PECRrs>;
171///PEC register
172pub mod pecr;
173/**RXDR (r) register accessor: Receive data register
174
175You can [`read`](crate::Reg::read) this register and get [`rxdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
176
177See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:RXDR)
178
179For information about available fields see [`mod@rxdr`]
180module*/
181pub type RXDR = crate::Reg<rxdr::RXDRrs>;
182///Receive data register
183pub mod rxdr;
184/**TXDR (rw) register accessor: Transmit data register
185
186You can [`read`](crate::Reg::read) this register and get [`txdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
187
188See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#I2C1:TXDR)
189
190For information about available fields see [`mod@txdr`]
191module*/
192pub type TXDR = crate::Reg<txdr::TXDRrs>;
193///Transmit data register
194pub mod txdr;
stm32g0_staging/stm32g0b0/i2c1.rs

stm32g0_staging/stm32g0b0/
i2c1.rs
