stm32g0_staging/stm32g0b0/gpiob/
bsrr.rs

1///Register `BSRR` writer
2pub type W = crate::W<BSRRrs>;
3/**Port x set pin %s
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum BS0W {
9    ///1: Sets the corresponding ODx bit
10    Set = 1,
11}
12impl From<BS0W> for bool {
13    #[inline(always)]
14    fn from(variant: BS0W) -> Self {
15        variant as u8 != 0
16    }
17}
18///Field `BS(0-15)` writer - Port x set pin %s
19pub type BS_W<'a, REG> = crate::BitWriter<'a, REG, BS0W>;
20impl<'a, REG> BS_W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    ///Sets the corresponding ODx bit
25    #[inline(always)]
26    pub fn set_(self) -> &'a mut crate::W<REG> {
27        self.variant(BS0W::Set)
28    }
29}
30/**Port x reset pin %s
31
32Value on reset: 0*/
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35pub enum BR0W {
36    ///1: Resets the corresponding ODx bit
37    Reset = 1,
38}
39impl From<BR0W> for bool {
40    #[inline(always)]
41    fn from(variant: BR0W) -> Self {
42        variant as u8 != 0
43    }
44}
45///Field `BR(0-15)` writer - Port x reset pin %s
46pub type BR_W<'a, REG> = crate::BitWriter<'a, REG, BR0W>;
47impl<'a, REG> BR_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    ///Resets the corresponding ODx bit
52    #[inline(always)]
53    pub fn reset(self) -> &'a mut crate::W<REG> {
54        self.variant(BR0W::Reset)
55    }
56}
57impl core::fmt::Debug for crate::generic::Reg<BSRRrs> {
58    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
59        write!(f, "(not readable)")
60    }
61}
62impl W {
63    ///Port x set pin (0-15)
64    ///
65    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BS0` field.</div>
66    #[inline(always)]
67    pub fn bs(&mut self, n: u8) -> BS_W<BSRRrs> {
68        #[allow(clippy::no_effect)] [(); 16][n as usize];
69        BS_W::new(self, n)
70    }
71    ///Bit 0 - Port x set pin 0
72    #[inline(always)]
73    pub fn bs0(&mut self) -> BS_W<BSRRrs> {
74        BS_W::new(self, 0)
75    }
76    ///Bit 1 - Port x set pin 1
77    #[inline(always)]
78    pub fn bs1(&mut self) -> BS_W<BSRRrs> {
79        BS_W::new(self, 1)
80    }
81    ///Bit 2 - Port x set pin 2
82    #[inline(always)]
83    pub fn bs2(&mut self) -> BS_W<BSRRrs> {
84        BS_W::new(self, 2)
85    }
86    ///Bit 3 - Port x set pin 3
87    #[inline(always)]
88    pub fn bs3(&mut self) -> BS_W<BSRRrs> {
89        BS_W::new(self, 3)
90    }
91    ///Bit 4 - Port x set pin 4
92    #[inline(always)]
93    pub fn bs4(&mut self) -> BS_W<BSRRrs> {
94        BS_W::new(self, 4)
95    }
96    ///Bit 5 - Port x set pin 5
97    #[inline(always)]
98    pub fn bs5(&mut self) -> BS_W<BSRRrs> {
99        BS_W::new(self, 5)
100    }
101    ///Bit 6 - Port x set pin 6
102    #[inline(always)]
103    pub fn bs6(&mut self) -> BS_W<BSRRrs> {
104        BS_W::new(self, 6)
105    }
106    ///Bit 7 - Port x set pin 7
107    #[inline(always)]
108    pub fn bs7(&mut self) -> BS_W<BSRRrs> {
109        BS_W::new(self, 7)
110    }
111    ///Bit 8 - Port x set pin 8
112    #[inline(always)]
113    pub fn bs8(&mut self) -> BS_W<BSRRrs> {
114        BS_W::new(self, 8)
115    }
116    ///Bit 9 - Port x set pin 9
117    #[inline(always)]
118    pub fn bs9(&mut self) -> BS_W<BSRRrs> {
119        BS_W::new(self, 9)
120    }
121    ///Bit 10 - Port x set pin 10
122    #[inline(always)]
123    pub fn bs10(&mut self) -> BS_W<BSRRrs> {
124        BS_W::new(self, 10)
125    }
126    ///Bit 11 - Port x set pin 11
127    #[inline(always)]
128    pub fn bs11(&mut self) -> BS_W<BSRRrs> {
129        BS_W::new(self, 11)
130    }
131    ///Bit 12 - Port x set pin 12
132    #[inline(always)]
133    pub fn bs12(&mut self) -> BS_W<BSRRrs> {
134        BS_W::new(self, 12)
135    }
136    ///Bit 13 - Port x set pin 13
137    #[inline(always)]
138    pub fn bs13(&mut self) -> BS_W<BSRRrs> {
139        BS_W::new(self, 13)
140    }
141    ///Bit 14 - Port x set pin 14
142    #[inline(always)]
143    pub fn bs14(&mut self) -> BS_W<BSRRrs> {
144        BS_W::new(self, 14)
145    }
146    ///Bit 15 - Port x set pin 15
147    #[inline(always)]
148    pub fn bs15(&mut self) -> BS_W<BSRRrs> {
149        BS_W::new(self, 15)
150    }
151    ///Port x reset pin (0-15)
152    ///
153    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `BR0` field.</div>
154    #[inline(always)]
155    pub fn br(&mut self, n: u8) -> BR_W<BSRRrs> {
156        #[allow(clippy::no_effect)] [(); 16][n as usize];
157        BR_W::new(self, n + 16)
158    }
159    ///Bit 16 - Port x reset pin 0
160    #[inline(always)]
161    pub fn br0(&mut self) -> BR_W<BSRRrs> {
162        BR_W::new(self, 16)
163    }
164    ///Bit 17 - Port x reset pin 1
165    #[inline(always)]
166    pub fn br1(&mut self) -> BR_W<BSRRrs> {
167        BR_W::new(self, 17)
168    }
169    ///Bit 18 - Port x reset pin 2
170    #[inline(always)]
171    pub fn br2(&mut self) -> BR_W<BSRRrs> {
172        BR_W::new(self, 18)
173    }
174    ///Bit 19 - Port x reset pin 3
175    #[inline(always)]
176    pub fn br3(&mut self) -> BR_W<BSRRrs> {
177        BR_W::new(self, 19)
178    }
179    ///Bit 20 - Port x reset pin 4
180    #[inline(always)]
181    pub fn br4(&mut self) -> BR_W<BSRRrs> {
182        BR_W::new(self, 20)
183    }
184    ///Bit 21 - Port x reset pin 5
185    #[inline(always)]
186    pub fn br5(&mut self) -> BR_W<BSRRrs> {
187        BR_W::new(self, 21)
188    }
189    ///Bit 22 - Port x reset pin 6
190    #[inline(always)]
191    pub fn br6(&mut self) -> BR_W<BSRRrs> {
192        BR_W::new(self, 22)
193    }
194    ///Bit 23 - Port x reset pin 7
195    #[inline(always)]
196    pub fn br7(&mut self) -> BR_W<BSRRrs> {
197        BR_W::new(self, 23)
198    }
199    ///Bit 24 - Port x reset pin 8
200    #[inline(always)]
201    pub fn br8(&mut self) -> BR_W<BSRRrs> {
202        BR_W::new(self, 24)
203    }
204    ///Bit 25 - Port x reset pin 9
205    #[inline(always)]
206    pub fn br9(&mut self) -> BR_W<BSRRrs> {
207        BR_W::new(self, 25)
208    }
209    ///Bit 26 - Port x reset pin 10
210    #[inline(always)]
211    pub fn br10(&mut self) -> BR_W<BSRRrs> {
212        BR_W::new(self, 26)
213    }
214    ///Bit 27 - Port x reset pin 11
215    #[inline(always)]
216    pub fn br11(&mut self) -> BR_W<BSRRrs> {
217        BR_W::new(self, 27)
218    }
219    ///Bit 28 - Port x reset pin 12
220    #[inline(always)]
221    pub fn br12(&mut self) -> BR_W<BSRRrs> {
222        BR_W::new(self, 28)
223    }
224    ///Bit 29 - Port x reset pin 13
225    #[inline(always)]
226    pub fn br13(&mut self) -> BR_W<BSRRrs> {
227        BR_W::new(self, 29)
228    }
229    ///Bit 30 - Port x reset pin 14
230    #[inline(always)]
231    pub fn br14(&mut self) -> BR_W<BSRRrs> {
232        BR_W::new(self, 30)
233    }
234    ///Bit 31 - Port x reset pin 15
235    #[inline(always)]
236    pub fn br15(&mut self) -> BR_W<BSRRrs> {
237        BR_W::new(self, 31)
238    }
239}
240/**GPIO port bit set/reset register
241
242You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bsrr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
243
244See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#GPIOB:BSRR)*/
245pub struct BSRRrs;
246impl crate::RegisterSpec for BSRRrs {
247    type Ux = u32;
248}
249///`write(|w| ..)` method takes [`bsrr::W`](W) writer structure
250impl crate::Writable for BSRRrs {
251    type Safety = crate::Unsafe;
252    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
253    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
254}
255///`reset()` method sets BSRR to value 0
256impl crate::Resettable for BSRRrs {
257    const RESET_VALUE: u32 = 0;
258}
stm32g0_staging/stm32g0b0/gpiob/bsrr.rs

stm32g0_staging/stm32g0b0/gpiob/
bsrr.rs
