stm32g0_staging/stm32g0b0/
adc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    isr: ISR,
6    ier: IER,
7    cr: CR,
8    cfgr1: CFGR1,
9    cfgr2: CFGR2,
10    smpr: SMPR,
11    _reserved6: [u8; 0x08],
12    awd1tr: AWD1TR,
13    awd2tr: AWD2TR,
14    _reserved_8_chselr0: [u8; 0x04],
15    awd3tr: AWD3TR,
16    _reserved10: [u8; 0x10],
17    dr: DR,
18    _reserved11: [u8; 0x5c],
19    awd2cr: AWD2CR,
20    awd3cr: AWD3CR,
21    _reserved13: [u8; 0x0c],
22    calfact: CALFACT,
23    _reserved14: [u8; 0x0250],
24    ccr: CCR,
25}
26impl RegisterBlock {
27    ///0x00 - ADC interrupt and status register
28    #[inline(always)]
29    pub const fn isr(&self) -> &ISR {
30        &self.isr
31    }
32    ///0x04 - ADC interrupt enable register
33    #[inline(always)]
34    pub const fn ier(&self) -> &IER {
35        &self.ier
36    }
37    ///0x08 - ADC control register
38    #[inline(always)]
39    pub const fn cr(&self) -> &CR {
40        &self.cr
41    }
42    ///0x0c - ADC configuration register 1
43    #[inline(always)]
44    pub const fn cfgr1(&self) -> &CFGR1 {
45        &self.cfgr1
46    }
47    ///0x10 - ADC configuration register 2
48    #[inline(always)]
49    pub const fn cfgr2(&self) -> &CFGR2 {
50        &self.cfgr2
51    }
52    ///0x14 - ADC sampling time register
53    #[inline(always)]
54    pub const fn smpr(&self) -> &SMPR {
55        &self.smpr
56    }
57    ///0x20 - ADC watchdog threshold register
58    #[inline(always)]
59    pub const fn awd1tr(&self) -> &AWD1TR {
60        &self.awd1tr
61    }
62    ///0x24 - ADC watchdog threshold register
63    #[inline(always)]
64    pub const fn awd2tr(&self) -> &AWD2TR {
65        &self.awd2tr
66    }
67    ///0x28 - channel selection register CHSELRMOD = 1 in ADC_CFGR1
68    #[inline(always)]
69    pub const fn chselr1(&self) -> &CHSELR1 {
70        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
71    }
72    ///0x28 - ADC channel selection register \[alternate\]
73    #[inline(always)]
74    pub const fn chselr0(&self) -> &CHSELR0 {
75        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
76    }
77    ///0x2c - ADC watchdog threshold register
78    #[inline(always)]
79    pub const fn awd3tr(&self) -> &AWD3TR {
80        &self.awd3tr
81    }
82    ///0x40 - ADC data register
83    #[inline(always)]
84    pub const fn dr(&self) -> &DR {
85        &self.dr
86    }
87    ///0xa0 - ADC Analog Watchdog 2 Configuration register
88    #[inline(always)]
89    pub const fn awd2cr(&self) -> &AWD2CR {
90        &self.awd2cr
91    }
92    ///0xa4 - ADC Analog Watchdog 3 Configuration register
93    #[inline(always)]
94    pub const fn awd3cr(&self) -> &AWD3CR {
95        &self.awd3cr
96    }
97    ///0xb4 - ADC Calibration factor
98    #[inline(always)]
99    pub const fn calfact(&self) -> &CALFACT {
100        &self.calfact
101    }
102    ///0x308 - ADC common configuration register
103    #[inline(always)]
104    pub const fn ccr(&self) -> &CCR {
105        &self.ccr
106    }
107}
108/**ISR (rw) register accessor: ADC interrupt and status register
109
110You can [`read`](crate::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
111
112See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:ISR)
113
114For information about available fields see [`mod@isr`]
115module*/
116pub type ISR = crate::Reg<isr::ISRrs>;
117///ADC interrupt and status register
118pub mod isr;
119/**IER (rw) register accessor: ADC interrupt enable register
120
121You can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
122
123See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:IER)
124
125For information about available fields see [`mod@ier`]
126module*/
127pub type IER = crate::Reg<ier::IERrs>;
128///ADC interrupt enable register
129pub mod ier;
130/**CR (rw) register accessor: ADC control register
131
132You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
133
134See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:CR)
135
136For information about available fields see [`mod@cr`]
137module*/
138pub type CR = crate::Reg<cr::CRrs>;
139///ADC control register
140pub mod cr;
141/**CFGR1 (rw) register accessor: ADC configuration register 1
142
143You can [`read`](crate::Reg::read) this register and get [`cfgr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
144
145See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:CFGR1)
146
147For information about available fields see [`mod@cfgr1`]
148module*/
149pub type CFGR1 = crate::Reg<cfgr1::CFGR1rs>;
150///ADC configuration register 1
151pub mod cfgr1;
152/**CFGR2 (rw) register accessor: ADC configuration register 2
153
154You can [`read`](crate::Reg::read) this register and get [`cfgr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
155
156See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:CFGR2)
157
158For information about available fields see [`mod@cfgr2`]
159module*/
160pub type CFGR2 = crate::Reg<cfgr2::CFGR2rs>;
161///ADC configuration register 2
162pub mod cfgr2;
163/**SMPR (rw) register accessor: ADC sampling time register
164
165You can [`read`](crate::Reg::read) this register and get [`smpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
166
167See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:SMPR)
168
169For information about available fields see [`mod@smpr`]
170module*/
171pub type SMPR = crate::Reg<smpr::SMPRrs>;
172///ADC sampling time register
173pub mod smpr;
174/**AWD1TR (rw) register accessor: ADC watchdog threshold register
175
176You can [`read`](crate::Reg::read) this register and get [`awd1tr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd1tr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
177
178See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:AWD1TR)
179
180For information about available fields see [`mod@awd1tr`]
181module*/
182pub type AWD1TR = crate::Reg<awd1tr::AWD1TRrs>;
183///ADC watchdog threshold register
184pub mod awd1tr;
185/**AWD2TR (rw) register accessor: ADC watchdog threshold register
186
187You can [`read`](crate::Reg::read) this register and get [`awd2tr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd2tr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
188
189See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:AWD2TR)
190
191For information about available fields see [`mod@awd2tr`]
192module*/
193pub type AWD2TR = crate::Reg<awd2tr::AWD2TRrs>;
194///ADC watchdog threshold register
195pub mod awd2tr;
196/**CHSELR0 (rw) register accessor: ADC channel selection register \[alternate\]
197
198You can [`read`](crate::Reg::read) this register and get [`chselr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chselr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
199
200See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:CHSELR0)
201
202For information about available fields see [`mod@chselr0`]
203module*/
204pub type CHSELR0 = crate::Reg<chselr0::CHSELR0rs>;
205///ADC channel selection register \[alternate\]
206pub mod chselr0;
207/**CHSELR1 (rw) register accessor: channel selection register CHSELRMOD = 1 in ADC_CFGR1
208
209You can [`read`](crate::Reg::read) this register and get [`chselr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chselr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
210
211See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:CHSELR1)
212
213For information about available fields see [`mod@chselr1`]
214module*/
215pub type CHSELR1 = crate::Reg<chselr1::CHSELR1rs>;
216///channel selection register CHSELRMOD = 1 in ADC_CFGR1
217pub mod chselr1;
218/**AWD3TR (rw) register accessor: ADC watchdog threshold register
219
220You can [`read`](crate::Reg::read) this register and get [`awd3tr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd3tr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
221
222See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:AWD3TR)
223
224For information about available fields see [`mod@awd3tr`]
225module*/
226pub type AWD3TR = crate::Reg<awd3tr::AWD3TRrs>;
227///ADC watchdog threshold register
228pub mod awd3tr;
229/**DR (r) register accessor: ADC data register
230
231You can [`read`](crate::Reg::read) this register and get [`dr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
232
233See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:DR)
234
235For information about available fields see [`mod@dr`]
236module*/
237pub type DR = crate::Reg<dr::DRrs>;
238///ADC data register
239pub mod dr;
240/**AWD2CR (rw) register accessor: ADC Analog Watchdog 2 Configuration register
241
242You can [`read`](crate::Reg::read) this register and get [`awd2cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd2cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
243
244See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:AWD2CR)
245
246For information about available fields see [`mod@awd2cr`]
247module*/
248pub type AWD2CR = crate::Reg<awd2cr::AWD2CRrs>;
249///ADC Analog Watchdog 2 Configuration register
250pub mod awd2cr;
251/**AWD3CR (rw) register accessor: ADC Analog Watchdog 3 Configuration register
252
253You can [`read`](crate::Reg::read) this register and get [`awd3cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd3cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
254
255See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:AWD3CR)
256
257For information about available fields see [`mod@awd3cr`]
258module*/
259pub type AWD3CR = crate::Reg<awd3cr::AWD3CRrs>;
260///ADC Analog Watchdog 3 Configuration register
261pub mod awd3cr;
262/**CALFACT (rw) register accessor: ADC Calibration factor
263
264You can [`read`](crate::Reg::read) this register and get [`calfact::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calfact::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
265
266See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:CALFACT)
267
268For information about available fields see [`mod@calfact`]
269module*/
270pub type CALFACT = crate::Reg<calfact::CALFACTrs>;
271///ADC Calibration factor
272pub mod calfact;
273/**CCR (rw) register accessor: ADC common configuration register
274
275You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
276
277See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#ADC:CCR)
278
279For information about available fields see [`mod@ccr`]
280module*/
281pub type CCR = crate::Reg<ccr::CCRrs>;
282///ADC common configuration register
283pub mod ccr;
stm32g0_staging/stm32g0b0/adc.rs

stm32g0_staging/stm32g0b0/
adc.rs
