stm32g0_staging/stm32g081/
rtc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    tr: TR,
6    dr: DR,
7    ssr: SSR,
8    icsr: ICSR,
9    prer: PRER,
10    wutr: WUTR,
11    cr: CR,
12    _reserved7: [u8; 0x08],
13    wpr: WPR,
14    calr: CALR,
15    shiftr: SHIFTR,
16    tstr: TSTR,
17    tsdr: TSDR,
18    tsssr: TSSSR,
19    _reserved13: [u8; 0x04],
20    alrmr: (),
21    _reserved14: [u8; 0x04],
22    alrmssr: (),
23    _reserved15: [u8; 0x0c],
24    sr: SR,
25    misr: MISR,
26    _reserved17: [u8; 0x04],
27    scr: SCR,
28    _reserved18: [u8; 0x0390],
29    hwcfgr: HWCFGR,
30    verr: VERR,
31    ipidr: IPIDR,
32    sidr: SIDR,
33}
34impl RegisterBlock {
35    ///0x00 - time register
36    #[inline(always)]
37    pub const fn tr(&self) -> &TR {
38        &self.tr
39    }
40    ///0x04 - date register
41    #[inline(always)]
42    pub const fn dr(&self) -> &DR {
43        &self.dr
44    }
45    ///0x08 - sub second register
46    #[inline(always)]
47    pub const fn ssr(&self) -> &SSR {
48        &self.ssr
49    }
50    ///0x0c - initialization and status register
51    #[inline(always)]
52    pub const fn icsr(&self) -> &ICSR {
53        &self.icsr
54    }
55    ///0x10 - prescaler register
56    #[inline(always)]
57    pub const fn prer(&self) -> &PRER {
58        &self.prer
59    }
60    ///0x14 - wakeup timer register
61    #[inline(always)]
62    pub const fn wutr(&self) -> &WUTR {
63        &self.wutr
64    }
65    ///0x18 - control register
66    #[inline(always)]
67    pub const fn cr(&self) -> &CR {
68        &self.cr
69    }
70    ///0x24 - write protection register
71    #[inline(always)]
72    pub const fn wpr(&self) -> &WPR {
73        &self.wpr
74    }
75    ///0x28 - calibration register
76    #[inline(always)]
77    pub const fn calr(&self) -> &CALR {
78        &self.calr
79    }
80    ///0x2c - shift control register
81    #[inline(always)]
82    pub const fn shiftr(&self) -> &SHIFTR {
83        &self.shiftr
84    }
85    ///0x30 - time stamp time register
86    #[inline(always)]
87    pub const fn tstr(&self) -> &TSTR {
88        &self.tstr
89    }
90    ///0x34 - time stamp date register
91    #[inline(always)]
92    pub const fn tsdr(&self) -> &TSDR {
93        &self.tsdr
94    }
95    ///0x38 - timestamp sub second register
96    #[inline(always)]
97    pub const fn tsssr(&self) -> &TSSSR {
98        &self.tsssr
99    }
100    ///0x40..0x48 - Alarm %s register
101    ///
102    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `ALRMAR` register.</div>
103    #[inline(always)]
104    pub const fn alrmr(&self, n: usize) -> &ALRMR {
105        #[allow(clippy::no_effect)] [(); 2][n];
106        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(64).add(8 * n).cast() }
107    }
108    ///Iterator for array of:
109    ///0x40..0x48 - Alarm %s register
110    #[inline(always)]
111    pub fn alrmr_iter(&self) -> impl Iterator<Item = &ALRMR> {
112        (0..2)
113            .map(move |n| unsafe {
114                &*core::ptr::from_ref(self).cast::<u8>().add(64).add(8 * n).cast()
115            })
116    }
117    ///0x40 - Alarm A register
118    #[inline(always)]
119    pub const fn alrmar(&self) -> &ALRMR {
120        self.alrmr(0)
121    }
122    ///0x48 - Alarm B register
123    #[inline(always)]
124    pub const fn alrmbr(&self) -> &ALRMR {
125        self.alrmr(1)
126    }
127    ///0x44..0x4c - Alarm %s sub-second register
128    ///
129    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `ALRMASSR` register.</div>
130    #[inline(always)]
131    pub const fn alrmssr(&self, n: usize) -> &ALRMSSR {
132        #[allow(clippy::no_effect)] [(); 2][n];
133        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(68).add(8 * n).cast() }
134    }
135    ///Iterator for array of:
136    ///0x44..0x4c - Alarm %s sub-second register
137    #[inline(always)]
138    pub fn alrmssr_iter(&self) -> impl Iterator<Item = &ALRMSSR> {
139        (0..2)
140            .map(move |n| unsafe {
141                &*core::ptr::from_ref(self).cast::<u8>().add(68).add(8 * n).cast()
142            })
143    }
144    ///0x44 - Alarm A sub-second register
145    #[inline(always)]
146    pub const fn alrmassr(&self) -> &ALRMSSR {
147        self.alrmssr(0)
148    }
149    ///0x4c - Alarm B sub-second register
150    #[inline(always)]
151    pub const fn alrmbssr(&self) -> &ALRMSSR {
152        self.alrmssr(1)
153    }
154    ///0x50 - status register
155    #[inline(always)]
156    pub const fn sr(&self) -> &SR {
157        &self.sr
158    }
159    ///0x54 - masked interrupt status register
160    #[inline(always)]
161    pub const fn misr(&self) -> &MISR {
162        &self.misr
163    }
164    ///0x5c - status clear register
165    #[inline(always)]
166    pub const fn scr(&self) -> &SCR {
167        &self.scr
168    }
169    ///0x3f0 - hardware configuration register
170    #[inline(always)]
171    pub const fn hwcfgr(&self) -> &HWCFGR {
172        &self.hwcfgr
173    }
174    ///0x3f4 - EXTI IP Version register
175    #[inline(always)]
176    pub const fn verr(&self) -> &VERR {
177        &self.verr
178    }
179    ///0x3f8 - EXTI Identification register
180    #[inline(always)]
181    pub const fn ipidr(&self) -> &IPIDR {
182        &self.ipidr
183    }
184    ///0x3fc - EXTI Size ID register
185    #[inline(always)]
186    pub const fn sidr(&self) -> &SIDR {
187        &self.sidr
188    }
189}
190/**TR (rw) register accessor: time register
191
192You can [`read`](crate::Reg::read) this register and get [`tr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
193
194See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:TR)
195
196For information about available fields see [`mod@tr`]
197module*/
198pub type TR = crate::Reg<tr::TRrs>;
199///time register
200pub mod tr;
201/**DR (rw) register accessor: date register
202
203You can [`read`](crate::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
204
205See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:DR)
206
207For information about available fields see [`mod@dr`]
208module*/
209pub type DR = crate::Reg<dr::DRrs>;
210///date register
211pub mod dr;
212/**SSR (r) register accessor: sub second register
213
214You can [`read`](crate::Reg::read) this register and get [`ssr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
215
216See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:SSR)
217
218For information about available fields see [`mod@ssr`]
219module*/
220pub type SSR = crate::Reg<ssr::SSRrs>;
221///sub second register
222pub mod ssr;
223/**ICSR (rw) register accessor: initialization and status register
224
225You can [`read`](crate::Reg::read) this register and get [`icsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
226
227See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:ICSR)
228
229For information about available fields see [`mod@icsr`]
230module*/
231pub type ICSR = crate::Reg<icsr::ICSRrs>;
232///initialization and status register
233pub mod icsr;
234/**PRER (rw) register accessor: prescaler register
235
236You can [`read`](crate::Reg::read) this register and get [`prer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
237
238See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:PRER)
239
240For information about available fields see [`mod@prer`]
241module*/
242pub type PRER = crate::Reg<prer::PRERrs>;
243///prescaler register
244pub mod prer;
245/**WUTR (rw) register accessor: wakeup timer register
246
247You can [`read`](crate::Reg::read) this register and get [`wutr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wutr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
248
249See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:WUTR)
250
251For information about available fields see [`mod@wutr`]
252module*/
253pub type WUTR = crate::Reg<wutr::WUTRrs>;
254///wakeup timer register
255pub mod wutr;
256/**CR (rw) register accessor: control register
257
258You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
259
260See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:CR)
261
262For information about available fields see [`mod@cr`]
263module*/
264pub type CR = crate::Reg<cr::CRrs>;
265///control register
266pub mod cr;
267/**WPR (w) register accessor: write protection register
268
269You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wpr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
270
271See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:WPR)
272
273For information about available fields see [`mod@wpr`]
274module*/
275pub type WPR = crate::Reg<wpr::WPRrs>;
276///write protection register
277pub mod wpr;
278/**CALR (rw) register accessor: calibration register
279
280You can [`read`](crate::Reg::read) this register and get [`calr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
281
282See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:CALR)
283
284For information about available fields see [`mod@calr`]
285module*/
286pub type CALR = crate::Reg<calr::CALRrs>;
287///calibration register
288pub mod calr;
289/**SHIFTR (w) register accessor: shift control register
290
291You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
292
293See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:SHIFTR)
294
295For information about available fields see [`mod@shiftr`]
296module*/
297pub type SHIFTR = crate::Reg<shiftr::SHIFTRrs>;
298///shift control register
299pub mod shiftr;
300pub use dr as tsdr;
301pub use ssr as tsssr;
302pub use tr as tstr;
303pub use DR as TSDR;
304pub use SSR as TSSSR;
305pub use TR as TSTR;
306/**ALRMR (rw) register accessor: Alarm %s register
307
308You can [`read`](crate::Reg::read) this register and get [`alrmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alrmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
309
310See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:ALRM[A]R)
311
312For information about available fields see [`mod@alrmr`]
313module*/
314pub type ALRMR = crate::Reg<alrmr::ALRMRrs>;
315///Alarm %s register
316pub mod alrmr;
317/**ALRMSSR (rw) register accessor: Alarm %s sub-second register
318
319You can [`read`](crate::Reg::read) this register and get [`alrmssr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alrmssr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
320
321See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:ALRM[A]SSR)
322
323For information about available fields see [`mod@alrmssr`]
324module*/
325pub type ALRMSSR = crate::Reg<alrmssr::ALRMSSRrs>;
326///Alarm %s sub-second register
327pub mod alrmssr;
328/**SR (r) register accessor: status register
329
330You can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
331
332See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:SR)
333
334For information about available fields see [`mod@sr`]
335module*/
336pub type SR = crate::Reg<sr::SRrs>;
337///status register
338pub mod sr;
339/**MISR (r) register accessor: masked interrupt status register
340
341You can [`read`](crate::Reg::read) this register and get [`misr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
342
343See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:MISR)
344
345For information about available fields see [`mod@misr`]
346module*/
347pub type MISR = crate::Reg<misr::MISRrs>;
348///masked interrupt status register
349pub mod misr;
350/**SCR (rw) register accessor: status clear register
351
352You can [`read`](crate::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
353
354See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:SCR)
355
356For information about available fields see [`mod@scr`]
357module*/
358pub type SCR = crate::Reg<scr::SCRrs>;
359///status clear register
360pub mod scr;
361/**HWCFGR (rw) register accessor: hardware configuration register
362
363You can [`read`](crate::Reg::read) this register and get [`hwcfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwcfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
364
365See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:HWCFGR)
366
367For information about available fields see [`mod@hwcfgr`]
368module*/
369pub type HWCFGR = crate::Reg<hwcfgr::HWCFGRrs>;
370///hardware configuration register
371pub mod hwcfgr;
372/**VERR (r) register accessor: EXTI IP Version register
373
374You can [`read`](crate::Reg::read) this register and get [`verr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
375
376See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:VERR)
377
378For information about available fields see [`mod@verr`]
379module*/
380pub type VERR = crate::Reg<verr::VERRrs>;
381///EXTI IP Version register
382pub mod verr;
383/**IPIDR (r) register accessor: EXTI Identification register
384
385You can [`read`](crate::Reg::read) this register and get [`ipidr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
386
387See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:IPIDR)
388
389For information about available fields see [`mod@ipidr`]
390module*/
391pub type IPIDR = crate::Reg<ipidr::IPIDRrs>;
392///EXTI Identification register
393pub mod ipidr;
394/**SIDR (r) register accessor: EXTI Size ID register
395
396You can [`read`](crate::Reg::read) this register and get [`sidr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
397
398See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G081.html#RTC:SIDR)
399
400For information about available fields see [`mod@sidr`]
401module*/
402pub type SIDR = crate::Reg<sidr::SIDRrs>;
403///EXTI Size ID register
404pub mod sidr;
stm32g0_staging/stm32g081/rtc.rs

stm32g0_staging/stm32g081/
rtc.rs
