stm32g0_staging/stm32g041/
tim2.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved_7_ccmr2: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    _reserved12: [u8; 0x04],
18    ccr: [CCR; 4],
19    _reserved13: [u8; 0x04],
20    dcr: DCR,
21    dmar: DMAR,
22    or1: OR1,
23    _reserved16: [u8; 0x0c],
24    af1: AF1,
25    _reserved17: [u8; 0x04],
26    tisel: TISEL,
27}
28impl RegisterBlock {
29    ///0x00 - control register 1
30    #[inline(always)]
31    pub const fn cr1(&self) -> &CR1 {
32        &self.cr1
33    }
34    ///0x04 - control register 2
35    #[inline(always)]
36    pub const fn cr2(&self) -> &CR2 {
37        &self.cr2
38    }
39    ///0x08 - slave mode control register
40    #[inline(always)]
41    pub const fn smcr(&self) -> &SMCR {
42        &self.smcr
43    }
44    ///0x0c - DMA/Interrupt enable register
45    #[inline(always)]
46    pub const fn dier(&self) -> &DIER {
47        &self.dier
48    }
49    ///0x10 - status register
50    #[inline(always)]
51    pub const fn sr(&self) -> &SR {
52        &self.sr
53    }
54    ///0x14 - event generation register
55    #[inline(always)]
56    pub const fn egr(&self) -> &EGR {
57        &self.egr
58    }
59    ///0x18 - capture/compare mode register 1 (input mode)
60    #[inline(always)]
61    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
62        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
63    }
64    ///0x18 - capture/compare mode register 1 (output mode)
65    #[inline(always)]
66    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
67        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
68    }
69    ///0x1c - capture/compare mode register 2 (input mode)
70    #[inline(always)]
71    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
72        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
73    }
74    ///0x1c - capture/compare mode register 2 (output mode)
75    #[inline(always)]
76    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
77        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
78    }
79    ///0x20 - capture/compare enable register
80    #[inline(always)]
81    pub const fn ccer(&self) -> &CCER {
82        &self.ccer
83    }
84    ///0x24 - counter
85    #[inline(always)]
86    pub const fn cnt(&self) -> &CNT {
87        &self.cnt
88    }
89    ///0x28 - prescaler
90    #[inline(always)]
91    pub const fn psc(&self) -> &PSC {
92        &self.psc
93    }
94    ///0x2c - auto-reload register
95    #[inline(always)]
96    pub const fn arr(&self) -> &ARR {
97        &self.arr
98    }
99    ///0x34..0x44 - capture/compare register
100    ///
101    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
102    #[inline(always)]
103    pub const fn ccr(&self, n: usize) -> &CCR {
104        &self.ccr[n]
105    }
106    ///Iterator for array of:
107    ///0x34..0x44 - capture/compare register
108    #[inline(always)]
109    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
110        self.ccr.iter()
111    }
112    ///0x34 - capture/compare register
113    #[inline(always)]
114    pub const fn ccr1(&self) -> &CCR {
115        self.ccr(0)
116    }
117    ///0x38 - capture/compare register
118    #[inline(always)]
119    pub const fn ccr2(&self) -> &CCR {
120        self.ccr(1)
121    }
122    ///0x3c - capture/compare register
123    #[inline(always)]
124    pub const fn ccr3(&self) -> &CCR {
125        self.ccr(2)
126    }
127    ///0x40 - capture/compare register
128    #[inline(always)]
129    pub const fn ccr4(&self) -> &CCR {
130        self.ccr(3)
131    }
132    ///0x48 - DMA control register
133    #[inline(always)]
134    pub const fn dcr(&self) -> &DCR {
135        &self.dcr
136    }
137    ///0x4c - DMA address for full transfer
138    #[inline(always)]
139    pub const fn dmar(&self) -> &DMAR {
140        &self.dmar
141    }
142    ///0x50 - TIM option register
143    #[inline(always)]
144    pub const fn or1(&self) -> &OR1 {
145        &self.or1
146    }
147    ///0x60 - TIM alternate function option register 1
148    #[inline(always)]
149    pub const fn af1(&self) -> &AF1 {
150        &self.af1
151    }
152    ///0x68 - TIM alternate function option register 1
153    #[inline(always)]
154    pub const fn tisel(&self) -> &TISEL {
155        &self.tisel
156    }
157}
158/**CR1 (rw) register accessor: control register 1
159
160You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:CR1)
163
164For information about available fields see [`mod@cr1`]
165module*/
166pub type CR1 = crate::Reg<cr1::CR1rs>;
167///control register 1
168pub mod cr1;
169/**CR2 (rw) register accessor: control register 2
170
171You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
172
173See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:CR2)
174
175For information about available fields see [`mod@cr2`]
176module*/
177pub type CR2 = crate::Reg<cr2::CR2rs>;
178///control register 2
179pub mod cr2;
180/**SMCR (rw) register accessor: slave mode control register
181
182You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
183
184See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:SMCR)
185
186For information about available fields see [`mod@smcr`]
187module*/
188pub type SMCR = crate::Reg<smcr::SMCRrs>;
189///slave mode control register
190pub mod smcr;
191/**DIER (rw) register accessor: DMA/Interrupt enable register
192
193You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
194
195See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:DIER)
196
197For information about available fields see [`mod@dier`]
198module*/
199pub type DIER = crate::Reg<dier::DIERrs>;
200///DMA/Interrupt enable register
201pub mod dier;
202/**SR (rw) register accessor: status register
203
204You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
205
206See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:SR)
207
208For information about available fields see [`mod@sr`]
209module*/
210pub type SR = crate::Reg<sr::SRrs>;
211///status register
212pub mod sr;
213/**EGR (w) register accessor: event generation register
214
215You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
216
217See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:EGR)
218
219For information about available fields see [`mod@egr`]
220module*/
221pub type EGR = crate::Reg<egr::EGRrs>;
222///event generation register
223pub mod egr;
224/**CCMR1_Output (rw) register accessor: capture/compare mode register 1 (output mode)
225
226You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
227
228See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:CCMR1_Output)
229
230For information about available fields see [`mod@ccmr1_output`]
231module*/
232#[doc(alias = "CCMR1_Output")]
233pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
234///capture/compare mode register 1 (output mode)
235pub mod ccmr1_output;
236/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
237
238You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
239
240See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:CCMR1_Input)
241
242For information about available fields see [`mod@ccmr1_input`]
243module*/
244#[doc(alias = "CCMR1_Input")]
245pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
246///capture/compare mode register 1 (input mode)
247pub mod ccmr1_input;
248/**CCMR2_Output (rw) register accessor: capture/compare mode register 2 (output mode)
249
250You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
251
252See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:CCMR2_Output)
253
254For information about available fields see [`mod@ccmr2_output`]
255module*/
256#[doc(alias = "CCMR2_Output")]
257pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUTrs>;
258///capture/compare mode register 2 (output mode)
259pub mod ccmr2_output;
260/**CCMR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)
261
262You can [`read`](crate::Reg::read) this register and get [`ccmr2_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
263
264See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:CCMR2_Input)
265
266For information about available fields see [`mod@ccmr2_input`]
267module*/
268#[doc(alias = "CCMR2_Input")]
269pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUTrs>;
270///capture/compare mode register 2 (input mode)
271pub mod ccmr2_input;
272/**CCER (rw) register accessor: capture/compare enable register
273
274You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
275
276See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:CCER)
277
278For information about available fields see [`mod@ccer`]
279module*/
280pub type CCER = crate::Reg<ccer::CCERrs>;
281///capture/compare enable register
282pub mod ccer;
283/**CNT (rw) register accessor: counter
284
285You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
286
287See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:CNT)
288
289For information about available fields see [`mod@cnt`]
290module*/
291pub type CNT = crate::Reg<cnt::CNTrs>;
292///counter
293pub mod cnt;
294/**PSC (rw) register accessor: prescaler
295
296You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
297
298See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:PSC)
299
300For information about available fields see [`mod@psc`]
301module*/
302pub type PSC = crate::Reg<psc::PSCrs>;
303///prescaler
304pub mod psc;
305/**ARR (rw) register accessor: auto-reload register
306
307You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
308
309See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:ARR)
310
311For information about available fields see [`mod@arr`]
312module*/
313pub type ARR = crate::Reg<arr::ARRrs>;
314///auto-reload register
315pub mod arr;
316/**CCR (rw) register accessor: capture/compare register
317
318You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
319
320See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:CCR[1])
321
322For information about available fields see [`mod@ccr`]
323module*/
324pub type CCR = crate::Reg<ccr::CCRrs>;
325///capture/compare register
326pub mod ccr;
327/**DCR (rw) register accessor: DMA control register
328
329You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
330
331See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:DCR)
332
333For information about available fields see [`mod@dcr`]
334module*/
335pub type DCR = crate::Reg<dcr::DCRrs>;
336///DMA control register
337pub mod dcr;
338/**DMAR (rw) register accessor: DMA address for full transfer
339
340You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
341
342See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:DMAR)
343
344For information about available fields see [`mod@dmar`]
345module*/
346pub type DMAR = crate::Reg<dmar::DMARrs>;
347///DMA address for full transfer
348pub mod dmar;
349/**OR1 (rw) register accessor: TIM option register
350
351You can [`read`](crate::Reg::read) this register and get [`or1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
352
353See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:OR1)
354
355For information about available fields see [`mod@or1`]
356module*/
357pub type OR1 = crate::Reg<or1::OR1rs>;
358///TIM option register
359pub mod or1;
360/**AF1 (rw) register accessor: TIM alternate function option register 1
361
362You can [`read`](crate::Reg::read) this register and get [`af1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`af1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
363
364See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:AF1)
365
366For information about available fields see [`mod@af1`]
367module*/
368pub type AF1 = crate::Reg<af1::AF1rs>;
369///TIM alternate function option register 1
370pub mod af1;
371/**TISEL (rw) register accessor: TIM alternate function option register 1
372
373You can [`read`](crate::Reg::read) this register and get [`tisel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
374
375See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G041.html#TIM2:TISEL)
376
377For information about available fields see [`mod@tisel`]
378module*/
379pub type TISEL = crate::Reg<tisel::TISELrs>;
380///TIM alternate function option register 1
381pub mod tisel;
stm32g0_staging/stm32g041/tim2.rs

stm32g0_staging/stm32g041/
tim2.rs
