stm32g0_staging/stm32g030/tim1/
tisel.rs

1///Register `TISEL` reader
2pub type R = crate::R<TISELrs>;
3///Register `TISEL` writer
4pub type W = crate::W<TISELrs>;
5/**Field `TI1SEL3_0` reader - selects TI1\[0\]
6to TI1\[15\]
7input*/
8pub type TI1SEL3_0_R = crate::FieldReader;
9/**Field `TI1SEL3_0` writer - selects TI1\[0\]
10to TI1\[15\]
11input*/
12pub type TI1SEL3_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13/**Field `TI2SEL3_0` reader - selects TI2\[0\]
14to TI2\[15\]
15input*/
16pub type TI2SEL3_0_R = crate::FieldReader;
17/**Field `TI2SEL3_0` writer - selects TI2\[0\]
18to TI2\[15\]
19input*/
20pub type TI2SEL3_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21/**Field `TI3SEL3_0` reader - selects TI3\[0\]
22to TI3\[15\]
23input*/
24pub type TI3SEL3_0_R = crate::FieldReader;
25/**Field `TI3SEL3_0` writer - selects TI3\[0\]
26to TI3\[15\]
27input*/
28pub type TI3SEL3_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29/**Field `TI4SEL3_0` reader - selects TI4\[0\]
30to TI4\[15\]
31input*/
32pub type TI4SEL3_0_R = crate::FieldReader;
33/**Field `TI4SEL3_0` writer - selects TI4\[0\]
34to TI4\[15\]
35input*/
36pub type TI4SEL3_0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
37impl R {
38    /**Bits 0:3 - selects TI1\[0\]
39to TI1\[15\]
40input*/
41    #[inline(always)]
42    pub fn ti1sel3_0(&self) -> TI1SEL3_0_R {
43        TI1SEL3_0_R::new((self.bits & 0x0f) as u8)
44    }
45    /**Bits 8:11 - selects TI2\[0\]
46to TI2\[15\]
47input*/
48    #[inline(always)]
49    pub fn ti2sel3_0(&self) -> TI2SEL3_0_R {
50        TI2SEL3_0_R::new(((self.bits >> 8) & 0x0f) as u8)
51    }
52    /**Bits 16:19 - selects TI3\[0\]
53to TI3\[15\]
54input*/
55    #[inline(always)]
56    pub fn ti3sel3_0(&self) -> TI3SEL3_0_R {
57        TI3SEL3_0_R::new(((self.bits >> 16) & 0x0f) as u8)
58    }
59    /**Bits 24:27 - selects TI4\[0\]
60to TI4\[15\]
61input*/
62    #[inline(always)]
63    pub fn ti4sel3_0(&self) -> TI4SEL3_0_R {
64        TI4SEL3_0_R::new(((self.bits >> 24) & 0x0f) as u8)
65    }
66}
67impl core::fmt::Debug for R {
68    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
69        f.debug_struct("TISEL")
70            .field("ti1sel3_0", &self.ti1sel3_0())
71            .field("ti2sel3_0", &self.ti2sel3_0())
72            .field("ti3sel3_0", &self.ti3sel3_0())
73            .field("ti4sel3_0", &self.ti4sel3_0())
74            .finish()
75    }
76}
77impl W {
78    /**Bits 0:3 - selects TI1\[0\]
79to TI1\[15\]
80input*/
81    #[inline(always)]
82    pub fn ti1sel3_0(&mut self) -> TI1SEL3_0_W<TISELrs> {
83        TI1SEL3_0_W::new(self, 0)
84    }
85    /**Bits 8:11 - selects TI2\[0\]
86to TI2\[15\]
87input*/
88    #[inline(always)]
89    pub fn ti2sel3_0(&mut self) -> TI2SEL3_0_W<TISELrs> {
90        TI2SEL3_0_W::new(self, 8)
91    }
92    /**Bits 16:19 - selects TI3\[0\]
93to TI3\[15\]
94input*/
95    #[inline(always)]
96    pub fn ti3sel3_0(&mut self) -> TI3SEL3_0_W<TISELrs> {
97        TI3SEL3_0_W::new(self, 16)
98    }
99    /**Bits 24:27 - selects TI4\[0\]
100to TI4\[15\]
101input*/
102    #[inline(always)]
103    pub fn ti4sel3_0(&mut self) -> TI4SEL3_0_W<TISELrs> {
104        TI4SEL3_0_W::new(self, 24)
105    }
106}
107/**TIM1 timer input selection register
108
109You can [`read`](crate::Reg::read) this register and get [`tisel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
110
111See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#TIM1:TISEL)*/
112pub struct TISELrs;
113impl crate::RegisterSpec for TISELrs {
114    type Ux = u32;
115}
116///`read()` method returns [`tisel::R`](R) reader structure
117impl crate::Readable for TISELrs {}
118///`write(|w| ..)` method takes [`tisel::W`](W) writer structure
119impl crate::Writable for TISELrs {
120    type Safety = crate::Unsafe;
121    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
122    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
123}
124///`reset()` method sets TISEL to value 0
125impl crate::Resettable for TISELrs {
126    const RESET_VALUE: u32 = 0;
127}
stm32g0_staging/stm32g030/tim1/tisel.rs

stm32g0_staging/stm32g030/tim1/
tisel.rs
