stm32g0_staging/stm32g030/rtc/
icsr.rs

1///Register `ICSR` reader
2pub type R = crate::R<ICSRrs>;
3///Register `ICSR` writer
4pub type W = crate::W<ICSRrs>;
5///Field `ALRWF(A,B)` reader - Alarm %s write flag
6pub type ALRWF_R = crate::BitReader;
7/**Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
8
9Value on reset: 1*/
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum WUTWFR {
13    ///0: Wakeup timer configuration update not allowed
14    UpdateNotAllowed = 0,
15    ///1: Wakeup timer configuration update allowed
16    UpdateAllowed = 1,
17}
18impl From<WUTWFR> for bool {
19    #[inline(always)]
20    fn from(variant: WUTWFR) -> Self {
21        variant as u8 != 0
22    }
23}
24///Field `WUTWF` reader - Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
25pub type WUTWF_R = crate::BitReader<WUTWFR>;
26impl WUTWF_R {
27    ///Get enumerated values variant
28    #[inline(always)]
29    pub const fn variant(&self) -> WUTWFR {
30        match self.bits {
31            false => WUTWFR::UpdateNotAllowed,
32            true => WUTWFR::UpdateAllowed,
33        }
34    }
35    ///Wakeup timer configuration update not allowed
36    #[inline(always)]
37    pub fn is_update_not_allowed(&self) -> bool {
38        *self == WUTWFR::UpdateNotAllowed
39    }
40    ///Wakeup timer configuration update allowed
41    #[inline(always)]
42    pub fn is_update_allowed(&self) -> bool {
43        *self == WUTWFR::UpdateAllowed
44    }
45}
46/**Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
47
48Value on reset: 0*/
49#[cfg_attr(feature = "defmt", derive(defmt::Format))]
50#[derive(Clone, Copy, Debug, PartialEq, Eq)]
51pub enum SHPFR {
52    ///0: No shift operation is pending
53    NoShiftPending = 0,
54    ///1: A shift operation is pending
55    ShiftPending = 1,
56}
57impl From<SHPFR> for bool {
58    #[inline(always)]
59    fn from(variant: SHPFR) -> Self {
60        variant as u8 != 0
61    }
62}
63///Field `SHPF` reader - Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
64pub type SHPF_R = crate::BitReader<SHPFR>;
65impl SHPF_R {
66    ///Get enumerated values variant
67    #[inline(always)]
68    pub const fn variant(&self) -> SHPFR {
69        match self.bits {
70            false => SHPFR::NoShiftPending,
71            true => SHPFR::ShiftPending,
72        }
73    }
74    ///No shift operation is pending
75    #[inline(always)]
76    pub fn is_no_shift_pending(&self) -> bool {
77        *self == SHPFR::NoShiftPending
78    }
79    ///A shift operation is pending
80    #[inline(always)]
81    pub fn is_shift_pending(&self) -> bool {
82        *self == SHPFR::ShiftPending
83    }
84}
85/**Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).
86
87Value on reset: 0*/
88#[cfg_attr(feature = "defmt", derive(defmt::Format))]
89#[derive(Clone, Copy, Debug, PartialEq, Eq)]
90pub enum INITSR {
91    ///0: Calendar has not been initialized
92    NotInitalized = 0,
93    ///1: Calendar has been initialized
94    Initalized = 1,
95}
96impl From<INITSR> for bool {
97    #[inline(always)]
98    fn from(variant: INITSR) -> Self {
99        variant as u8 != 0
100    }
101}
102///Field `INITS` reader - Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).
103pub type INITS_R = crate::BitReader<INITSR>;
104impl INITS_R {
105    ///Get enumerated values variant
106    #[inline(always)]
107    pub const fn variant(&self) -> INITSR {
108        match self.bits {
109            false => INITSR::NotInitalized,
110            true => INITSR::Initalized,
111        }
112    }
113    ///Calendar has not been initialized
114    #[inline(always)]
115    pub fn is_not_initalized(&self) -> bool {
116        *self == INITSR::NotInitalized
117    }
118    ///Calendar has been initialized
119    #[inline(always)]
120    pub fn is_initalized(&self) -> bool {
121        *self == INITSR::Initalized
122    }
123}
124/**Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
125
126Value on reset: 0*/
127#[cfg_attr(feature = "defmt", derive(defmt::Format))]
128#[derive(Clone, Copy, Debug, PartialEq, Eq)]
129pub enum RSFR {
130    ///0: Calendar shadow registers not yet synchronized
131    NotSynced = 0,
132    ///1: Calendar shadow registers synchronized
133    Synced = 1,
134}
135impl From<RSFR> for bool {
136    #[inline(always)]
137    fn from(variant: RSFR) -> Self {
138        variant as u8 != 0
139    }
140}
141///Field `RSF` reader - Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
142pub type RSF_R = crate::BitReader<RSFR>;
143impl RSF_R {
144    ///Get enumerated values variant
145    #[inline(always)]
146    pub const fn variant(&self) -> RSFR {
147        match self.bits {
148            false => RSFR::NotSynced,
149            true => RSFR::Synced,
150        }
151    }
152    ///Calendar shadow registers not yet synchronized
153    #[inline(always)]
154    pub fn is_not_synced(&self) -> bool {
155        *self == RSFR::NotSynced
156    }
157    ///Calendar shadow registers synchronized
158    #[inline(always)]
159    pub fn is_synced(&self) -> bool {
160        *self == RSFR::Synced
161    }
162}
163/**Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
164
165Value on reset: 0*/
166#[cfg_attr(feature = "defmt", derive(defmt::Format))]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum RSFW {
169    ///0: This flag is cleared by software by writing 0
170    Clear = 0,
171}
172impl From<RSFW> for bool {
173    #[inline(always)]
174    fn from(variant: RSFW) -> Self {
175        variant as u8 != 0
176    }
177}
178///Field `RSF` writer - Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
179pub type RSF_W<'a, REG> = crate::BitWriter0C<'a, REG, RSFW>;
180impl<'a, REG> RSF_W<'a, REG>
181where
182    REG: crate::Writable + crate::RegisterSpec,
183{
184    ///This flag is cleared by software by writing 0
185    #[inline(always)]
186    pub fn clear(self) -> &'a mut crate::W<REG> {
187        self.variant(RSFW::Clear)
188    }
189}
190/**Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
191
192Value on reset: 0*/
193#[cfg_attr(feature = "defmt", derive(defmt::Format))]
194#[derive(Clone, Copy, Debug, PartialEq, Eq)]
195pub enum INITFR {
196    ///0: Calendar registers update is not allowed
197    NotAllowed = 0,
198    ///1: Calendar registers update is allowed
199    Allowed = 1,
200}
201impl From<INITFR> for bool {
202    #[inline(always)]
203    fn from(variant: INITFR) -> Self {
204        variant as u8 != 0
205    }
206}
207///Field `INITF` reader - Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
208pub type INITF_R = crate::BitReader<INITFR>;
209impl INITF_R {
210    ///Get enumerated values variant
211    #[inline(always)]
212    pub const fn variant(&self) -> INITFR {
213        match self.bits {
214            false => INITFR::NotAllowed,
215            true => INITFR::Allowed,
216        }
217    }
218    ///Calendar registers update is not allowed
219    #[inline(always)]
220    pub fn is_not_allowed(&self) -> bool {
221        *self == INITFR::NotAllowed
222    }
223    ///Calendar registers update is allowed
224    #[inline(always)]
225    pub fn is_allowed(&self) -> bool {
226        *self == INITFR::Allowed
227    }
228}
229/**Initialization mode
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum INIT {
235    ///0: Free running mode
236    FreeRunningMode = 0,
237    ///1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
238    InitMode = 1,
239}
240impl From<INIT> for bool {
241    #[inline(always)]
242    fn from(variant: INIT) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `INIT` reader - Initialization mode
247pub type INIT_R = crate::BitReader<INIT>;
248impl INIT_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> INIT {
252        match self.bits {
253            false => INIT::FreeRunningMode,
254            true => INIT::InitMode,
255        }
256    }
257    ///Free running mode
258    #[inline(always)]
259    pub fn is_free_running_mode(&self) -> bool {
260        *self == INIT::FreeRunningMode
261    }
262    ///Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
263    #[inline(always)]
264    pub fn is_init_mode(&self) -> bool {
265        *self == INIT::InitMode
266    }
267}
268///Field `INIT` writer - Initialization mode
269pub type INIT_W<'a, REG> = crate::BitWriter<'a, REG, INIT>;
270impl<'a, REG> INIT_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///Free running mode
275    #[inline(always)]
276    pub fn free_running_mode(self) -> &'a mut crate::W<REG> {
277        self.variant(INIT::FreeRunningMode)
278    }
279    ///Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
280    #[inline(always)]
281    pub fn init_mode(self) -> &'a mut crate::W<REG> {
282        self.variant(INIT::InitMode)
283    }
284}
285/**Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to .
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum RECALPFR {
291    ///1: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
292    Pending = 1,
293}
294impl From<RECALPFR> for bool {
295    #[inline(always)]
296    fn from(variant: RECALPFR) -> Self {
297        variant as u8 != 0
298    }
299}
300///Field `RECALPF` reader - Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to .
301pub type RECALPF_R = crate::BitReader<RECALPFR>;
302impl RECALPF_R {
303    ///Get enumerated values variant
304    #[inline(always)]
305    pub const fn variant(&self) -> Option<RECALPFR> {
306        match self.bits {
307            true => Some(RECALPFR::Pending),
308            _ => None,
309        }
310    }
311    ///The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0
312    #[inline(always)]
313    pub fn is_pending(&self) -> bool {
314        *self == RECALPFR::Pending
315    }
316}
317impl R {
318    ///Alarm (A,B) write flag
319    ///
320    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `ALRAWF` field.</div>
321    #[inline(always)]
322    pub fn alrwf(&self, n: u8) -> ALRWF_R {
323        #[allow(clippy::no_effect)] [(); 2][n as usize];
324        ALRWF_R::new(((self.bits >> n) & 1) != 0)
325    }
326    ///Iterator for array of:
327    ///Alarm (A,B) write flag
328    #[inline(always)]
329    pub fn alrwf_iter(&self) -> impl Iterator<Item = ALRWF_R> + '_ {
330        (0..2).map(move |n| ALRWF_R::new(((self.bits >> n) & 1) != 0))
331    }
332    ///Bit 0 - Alarm A write flag
333    #[inline(always)]
334    pub fn alrawf(&self) -> ALRWF_R {
335        ALRWF_R::new((self.bits & 1) != 0)
336    }
337    ///Bit 1 - Alarm B write flag
338    #[inline(always)]
339    pub fn alrbwf(&self) -> ALRWF_R {
340        ALRWF_R::new(((self.bits >> 1) & 1) != 0)
341    }
342    ///Bit 2 - Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
343    #[inline(always)]
344    pub fn wutwf(&self) -> WUTWF_R {
345        WUTWF_R::new(((self.bits >> 2) & 1) != 0)
346    }
347    ///Bit 3 - Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
348    #[inline(always)]
349    pub fn shpf(&self) -> SHPF_R {
350        SHPF_R::new(((self.bits >> 3) & 1) != 0)
351    }
352    ///Bit 4 - Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).
353    #[inline(always)]
354    pub fn inits(&self) -> INITS_R {
355        INITS_R::new(((self.bits >> 4) & 1) != 0)
356    }
357    ///Bit 5 - Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
358    #[inline(always)]
359    pub fn rsf(&self) -> RSF_R {
360        RSF_R::new(((self.bits >> 5) & 1) != 0)
361    }
362    ///Bit 6 - Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
363    #[inline(always)]
364    pub fn initf(&self) -> INITF_R {
365        INITF_R::new(((self.bits >> 6) & 1) != 0)
366    }
367    ///Bit 7 - Initialization mode
368    #[inline(always)]
369    pub fn init(&self) -> INIT_R {
370        INIT_R::new(((self.bits >> 7) & 1) != 0)
371    }
372    ///Bit 16 - Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to .
373    #[inline(always)]
374    pub fn recalpf(&self) -> RECALPF_R {
375        RECALPF_R::new(((self.bits >> 16) & 1) != 0)
376    }
377}
378impl core::fmt::Debug for R {
379    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
380        f.debug_struct("ICSR")
381            .field("alrawf", &self.alrawf())
382            .field("alrbwf", &self.alrbwf())
383            .field("wutwf", &self.wutwf())
384            .field("shpf", &self.shpf())
385            .field("inits", &self.inits())
386            .field("rsf", &self.rsf())
387            .field("initf", &self.initf())
388            .field("init", &self.init())
389            .field("recalpf", &self.recalpf())
390            .finish()
391    }
392}
393impl W {
394    ///Bit 5 - Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
395    #[inline(always)]
396    pub fn rsf(&mut self) -> RSF_W<ICSRrs> {
397        RSF_W::new(self, 5)
398    }
399    ///Bit 7 - Initialization mode
400    #[inline(always)]
401    pub fn init(&mut self) -> INIT_W<ICSRrs> {
402        INIT_W::new(self, 7)
403    }
404}
405/**RTC initialization control and status register
406
407You can [`read`](crate::Reg::read) this register and get [`icsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
408
409See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:ICSR)*/
410pub struct ICSRrs;
411impl crate::RegisterSpec for ICSRrs {
412    type Ux = u32;
413}
414///`read()` method returns [`icsr::R`](R) reader structure
415impl crate::Readable for ICSRrs {}
416///`write(|w| ..)` method takes [`icsr::W`](W) writer structure
417impl crate::Writable for ICSRrs {
418    type Safety = crate::Unsafe;
419    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x20;
420    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
421}
422///`reset()` method sets ICSR to value 0x07
423impl crate::Resettable for ICSRrs {
424    const RESET_VALUE: u32 = 0x07;
425}
stm32g0_staging/stm32g030/rtc/icsr.rs

stm32g0_staging/stm32g030/rtc/
icsr.rs
