stm32g0_staging/stm32g030/
rtc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    tr: TR,
6    dr: DR,
7    ssr: SSR,
8    icsr: ICSR,
9    prer: PRER,
10    wutr: WUTR,
11    cr: CR,
12    _reserved7: [u8; 0x08],
13    wpr: WPR,
14    calr: CALR,
15    shiftr: SHIFTR,
16    tstr: TSTR,
17    tsdr: TSDR,
18    tsssr: TSSSR,
19    _reserved13: [u8; 0x04],
20    alrmr: (),
21    _reserved14: [u8; 0x04],
22    alrmssr: (),
23    _reserved15: [u8; 0x0c],
24    sr: SR,
25    misr: MISR,
26    _reserved17: [u8; 0x04],
27    scr: SCR,
28}
29impl RegisterBlock {
30    ///0x00 - RTC time register
31    #[inline(always)]
32    pub const fn tr(&self) -> &TR {
33        &self.tr
34    }
35    ///0x04 - RTC date register
36    #[inline(always)]
37    pub const fn dr(&self) -> &DR {
38        &self.dr
39    }
40    ///0x08 - RTC sub second register
41    #[inline(always)]
42    pub const fn ssr(&self) -> &SSR {
43        &self.ssr
44    }
45    ///0x0c - RTC initialization control and status register
46    #[inline(always)]
47    pub const fn icsr(&self) -> &ICSR {
48        &self.icsr
49    }
50    ///0x10 - RTC prescaler register
51    #[inline(always)]
52    pub const fn prer(&self) -> &PRER {
53        &self.prer
54    }
55    ///0x14 - RTC wakeup timer register
56    #[inline(always)]
57    pub const fn wutr(&self) -> &WUTR {
58        &self.wutr
59    }
60    ///0x18 - control register
61    #[inline(always)]
62    pub const fn cr(&self) -> &CR {
63        &self.cr
64    }
65    ///0x24 - write protection register
66    #[inline(always)]
67    pub const fn wpr(&self) -> &WPR {
68        &self.wpr
69    }
70    ///0x28 - RTC calibration register
71    #[inline(always)]
72    pub const fn calr(&self) -> &CALR {
73        &self.calr
74    }
75    ///0x2c - RTC shift control register
76    #[inline(always)]
77    pub const fn shiftr(&self) -> &SHIFTR {
78        &self.shiftr
79    }
80    ///0x30 - RTC timestamp time register
81    #[inline(always)]
82    pub const fn tstr(&self) -> &TSTR {
83        &self.tstr
84    }
85    ///0x34 - RTC timestamp date register
86    #[inline(always)]
87    pub const fn tsdr(&self) -> &TSDR {
88        &self.tsdr
89    }
90    ///0x38 - RTC timestamp sub second register
91    #[inline(always)]
92    pub const fn tsssr(&self) -> &TSSSR {
93        &self.tsssr
94    }
95    ///0x40..0x48 - Alarm %s register
96    ///
97    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `ALRMAR` register.</div>
98    #[inline(always)]
99    pub const fn alrmr(&self, n: usize) -> &ALRMR {
100        #[allow(clippy::no_effect)] [(); 2][n];
101        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(64).add(8 * n).cast() }
102    }
103    ///Iterator for array of:
104    ///0x40..0x48 - Alarm %s register
105    #[inline(always)]
106    pub fn alrmr_iter(&self) -> impl Iterator<Item = &ALRMR> {
107        (0..2)
108            .map(move |n| unsafe {
109                &*core::ptr::from_ref(self).cast::<u8>().add(64).add(8 * n).cast()
110            })
111    }
112    ///0x40 - Alarm A register
113    #[inline(always)]
114    pub const fn alrmar(&self) -> &ALRMR {
115        self.alrmr(0)
116    }
117    ///0x48 - Alarm B register
118    #[inline(always)]
119    pub const fn alrmbr(&self) -> &ALRMR {
120        self.alrmr(1)
121    }
122    ///0x44..0x4c - Alarm %s sub-second register
123    ///
124    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `ALRMASSR` register.</div>
125    #[inline(always)]
126    pub const fn alrmssr(&self, n: usize) -> &ALRMSSR {
127        #[allow(clippy::no_effect)] [(); 2][n];
128        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(68).add(8 * n).cast() }
129    }
130    ///Iterator for array of:
131    ///0x44..0x4c - Alarm %s sub-second register
132    #[inline(always)]
133    pub fn alrmssr_iter(&self) -> impl Iterator<Item = &ALRMSSR> {
134        (0..2)
135            .map(move |n| unsafe {
136                &*core::ptr::from_ref(self).cast::<u8>().add(68).add(8 * n).cast()
137            })
138    }
139    ///0x44 - Alarm A sub-second register
140    #[inline(always)]
141    pub const fn alrmassr(&self) -> &ALRMSSR {
142        self.alrmssr(0)
143    }
144    ///0x4c - Alarm B sub-second register
145    #[inline(always)]
146    pub const fn alrmbssr(&self) -> &ALRMSSR {
147        self.alrmssr(1)
148    }
149    ///0x50 - RTC status register
150    #[inline(always)]
151    pub const fn sr(&self) -> &SR {
152        &self.sr
153    }
154    ///0x54 - RTC masked interrupt status register
155    #[inline(always)]
156    pub const fn misr(&self) -> &MISR {
157        &self.misr
158    }
159    ///0x5c - RTC status clear register
160    #[inline(always)]
161    pub const fn scr(&self) -> &SCR {
162        &self.scr
163    }
164}
165/**TR (rw) register accessor: RTC time register
166
167You can [`read`](crate::Reg::read) this register and get [`tr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
168
169See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:TR)
170
171For information about available fields see [`mod@tr`]
172module*/
173pub type TR = crate::Reg<tr::TRrs>;
174///RTC time register
175pub mod tr;
176/**DR (rw) register accessor: RTC date register
177
178You can [`read`](crate::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
179
180See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:DR)
181
182For information about available fields see [`mod@dr`]
183module*/
184pub type DR = crate::Reg<dr::DRrs>;
185///RTC date register
186pub mod dr;
187/**SSR (r) register accessor: RTC sub second register
188
189You can [`read`](crate::Reg::read) this register and get [`ssr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
190
191See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:SSR)
192
193For information about available fields see [`mod@ssr`]
194module*/
195pub type SSR = crate::Reg<ssr::SSRrs>;
196///RTC sub second register
197pub mod ssr;
198/**ICSR (rw) register accessor: RTC initialization control and status register
199
200You can [`read`](crate::Reg::read) this register and get [`icsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
201
202See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:ICSR)
203
204For information about available fields see [`mod@icsr`]
205module*/
206pub type ICSR = crate::Reg<icsr::ICSRrs>;
207///RTC initialization control and status register
208pub mod icsr;
209/**PRER (rw) register accessor: RTC prescaler register
210
211You can [`read`](crate::Reg::read) this register and get [`prer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
212
213See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:PRER)
214
215For information about available fields see [`mod@prer`]
216module*/
217pub type PRER = crate::Reg<prer::PRERrs>;
218///RTC prescaler register
219pub mod prer;
220/**WUTR (rw) register accessor: RTC wakeup timer register
221
222You can [`read`](crate::Reg::read) this register and get [`wutr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wutr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
223
224See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:WUTR)
225
226For information about available fields see [`mod@wutr`]
227module*/
228pub type WUTR = crate::Reg<wutr::WUTRrs>;
229///RTC wakeup timer register
230pub mod wutr;
231/**CR (rw) register accessor: control register
232
233You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
234
235See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:CR)
236
237For information about available fields see [`mod@cr`]
238module*/
239pub type CR = crate::Reg<cr::CRrs>;
240///control register
241pub mod cr;
242/**WPR (w) register accessor: write protection register
243
244You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wpr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
245
246See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:WPR)
247
248For information about available fields see [`mod@wpr`]
249module*/
250pub type WPR = crate::Reg<wpr::WPRrs>;
251///write protection register
252pub mod wpr;
253/**CALR (rw) register accessor: RTC calibration register
254
255You can [`read`](crate::Reg::read) this register and get [`calr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
256
257See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:CALR)
258
259For information about available fields see [`mod@calr`]
260module*/
261pub type CALR = crate::Reg<calr::CALRrs>;
262///RTC calibration register
263pub mod calr;
264/**SHIFTR (w) register accessor: RTC shift control register
265
266You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
267
268See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:SHIFTR)
269
270For information about available fields see [`mod@shiftr`]
271module*/
272pub type SHIFTR = crate::Reg<shiftr::SHIFTRrs>;
273///RTC shift control register
274pub mod shiftr;
275pub use dr as tsdr;
276pub use ssr as tsssr;
277pub use tr as tstr;
278pub use DR as TSDR;
279pub use SSR as TSSSR;
280pub use TR as TSTR;
281/**ALRMR (rw) register accessor: Alarm %s register
282
283You can [`read`](crate::Reg::read) this register and get [`alrmr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alrmr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
284
285See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:ALRM[A]R)
286
287For information about available fields see [`mod@alrmr`]
288module*/
289pub type ALRMR = crate::Reg<alrmr::ALRMRrs>;
290///Alarm %s register
291pub mod alrmr;
292/**ALRMSSR (rw) register accessor: Alarm %s sub-second register
293
294You can [`read`](crate::Reg::read) this register and get [`alrmssr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alrmssr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
295
296See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:ALRM[A]SSR)
297
298For information about available fields see [`mod@alrmssr`]
299module*/
300pub type ALRMSSR = crate::Reg<alrmssr::ALRMSSRrs>;
301///Alarm %s sub-second register
302pub mod alrmssr;
303/**SR (r) register accessor: RTC status register
304
305You can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
306
307See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:SR)
308
309For information about available fields see [`mod@sr`]
310module*/
311pub type SR = crate::Reg<sr::SRrs>;
312///RTC status register
313pub mod sr;
314/**MISR (r) register accessor: RTC masked interrupt status register
315
316You can [`read`](crate::Reg::read) this register and get [`misr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
317
318See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:MISR)
319
320For information about available fields see [`mod@misr`]
321module*/
322pub type MISR = crate::Reg<misr::MISRrs>;
323///RTC masked interrupt status register
324pub mod misr;
325/**SCR (w) register accessor: RTC status clear register
326
327You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
328
329See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#RTC:SCR)
330
331For information about available fields see [`mod@scr`]
332module*/
333pub type SCR = crate::Reg<scr::SCRrs>;
334///RTC status clear register
335pub mod scr;
stm32g0_staging/stm32g030/rtc.rs

stm32g0_staging/stm32g030/
rtc.rs
