stm32g0_staging/stm32g030/gpiob/
ospeedr.rs

1///Register `OSPEEDR` reader
2pub type R = crate::R<OSPEEDRrs>;
3///Register `OSPEEDR` writer
4pub type W = crate::W<OSPEEDRrs>;
5/**Port x configuration pin %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum OSPEEDR0 {
12    ///0: Low speed
13    LowSpeed = 0,
14    ///1: Medium speed
15    MediumSpeed = 1,
16    ///2: High speed
17    HighSpeed = 2,
18    ///3: Very high speed
19    VeryHighSpeed = 3,
20}
21impl From<OSPEEDR0> for u8 {
22    #[inline(always)]
23    fn from(variant: OSPEEDR0) -> Self {
24        variant as _
25    }
26}
27impl crate::FieldSpec for OSPEEDR0 {
28    type Ux = u8;
29}
30impl crate::IsEnum for OSPEEDR0 {}
31///Field `OSPEEDR(0-15)` reader - Port x configuration pin %s
32pub type OSPEEDR_R = crate::FieldReader<OSPEEDR0>;
33impl OSPEEDR_R {
34    ///Get enumerated values variant
35    #[inline(always)]
36    pub const fn variant(&self) -> OSPEEDR0 {
37        match self.bits {
38            0 => OSPEEDR0::LowSpeed,
39            1 => OSPEEDR0::MediumSpeed,
40            2 => OSPEEDR0::HighSpeed,
41            3 => OSPEEDR0::VeryHighSpeed,
42            _ => unreachable!(),
43        }
44    }
45    ///Low speed
46    #[inline(always)]
47    pub fn is_low_speed(&self) -> bool {
48        *self == OSPEEDR0::LowSpeed
49    }
50    ///Medium speed
51    #[inline(always)]
52    pub fn is_medium_speed(&self) -> bool {
53        *self == OSPEEDR0::MediumSpeed
54    }
55    ///High speed
56    #[inline(always)]
57    pub fn is_high_speed(&self) -> bool {
58        *self == OSPEEDR0::HighSpeed
59    }
60    ///Very high speed
61    #[inline(always)]
62    pub fn is_very_high_speed(&self) -> bool {
63        *self == OSPEEDR0::VeryHighSpeed
64    }
65}
66///Field `OSPEEDR(0-15)` writer - Port x configuration pin %s
67pub type OSPEEDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OSPEEDR0, crate::Safe>;
68impl<'a, REG> OSPEEDR_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    ///Low speed
74    #[inline(always)]
75    pub fn low_speed(self) -> &'a mut crate::W<REG> {
76        self.variant(OSPEEDR0::LowSpeed)
77    }
78    ///Medium speed
79    #[inline(always)]
80    pub fn medium_speed(self) -> &'a mut crate::W<REG> {
81        self.variant(OSPEEDR0::MediumSpeed)
82    }
83    ///High speed
84    #[inline(always)]
85    pub fn high_speed(self) -> &'a mut crate::W<REG> {
86        self.variant(OSPEEDR0::HighSpeed)
87    }
88    ///Very high speed
89    #[inline(always)]
90    pub fn very_high_speed(self) -> &'a mut crate::W<REG> {
91        self.variant(OSPEEDR0::VeryHighSpeed)
92    }
93}
94impl R {
95    ///Port x configuration pin (0-15)
96    ///
97    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OSPEEDR0` field.</div>
98    #[inline(always)]
99    pub fn ospeedr(&self, n: u8) -> OSPEEDR_R {
100        #[allow(clippy::no_effect)] [(); 16][n as usize];
101        OSPEEDR_R::new(((self.bits >> (n * 2)) & 3) as u8)
102    }
103    ///Iterator for array of:
104    ///Port x configuration pin (0-15)
105    #[inline(always)]
106    pub fn ospeedr_iter(&self) -> impl Iterator<Item = OSPEEDR_R> + '_ {
107        (0..16).map(move |n| OSPEEDR_R::new(((self.bits >> (n * 2)) & 3) as u8))
108    }
109    ///Bits 0:1 - Port x configuration pin 0
110    #[inline(always)]
111    pub fn ospeedr0(&self) -> OSPEEDR_R {
112        OSPEEDR_R::new((self.bits & 3) as u8)
113    }
114    ///Bits 2:3 - Port x configuration pin 1
115    #[inline(always)]
116    pub fn ospeedr1(&self) -> OSPEEDR_R {
117        OSPEEDR_R::new(((self.bits >> 2) & 3) as u8)
118    }
119    ///Bits 4:5 - Port x configuration pin 2
120    #[inline(always)]
121    pub fn ospeedr2(&self) -> OSPEEDR_R {
122        OSPEEDR_R::new(((self.bits >> 4) & 3) as u8)
123    }
124    ///Bits 6:7 - Port x configuration pin 3
125    #[inline(always)]
126    pub fn ospeedr3(&self) -> OSPEEDR_R {
127        OSPEEDR_R::new(((self.bits >> 6) & 3) as u8)
128    }
129    ///Bits 8:9 - Port x configuration pin 4
130    #[inline(always)]
131    pub fn ospeedr4(&self) -> OSPEEDR_R {
132        OSPEEDR_R::new(((self.bits >> 8) & 3) as u8)
133    }
134    ///Bits 10:11 - Port x configuration pin 5
135    #[inline(always)]
136    pub fn ospeedr5(&self) -> OSPEEDR_R {
137        OSPEEDR_R::new(((self.bits >> 10) & 3) as u8)
138    }
139    ///Bits 12:13 - Port x configuration pin 6
140    #[inline(always)]
141    pub fn ospeedr6(&self) -> OSPEEDR_R {
142        OSPEEDR_R::new(((self.bits >> 12) & 3) as u8)
143    }
144    ///Bits 14:15 - Port x configuration pin 7
145    #[inline(always)]
146    pub fn ospeedr7(&self) -> OSPEEDR_R {
147        OSPEEDR_R::new(((self.bits >> 14) & 3) as u8)
148    }
149    ///Bits 16:17 - Port x configuration pin 8
150    #[inline(always)]
151    pub fn ospeedr8(&self) -> OSPEEDR_R {
152        OSPEEDR_R::new(((self.bits >> 16) & 3) as u8)
153    }
154    ///Bits 18:19 - Port x configuration pin 9
155    #[inline(always)]
156    pub fn ospeedr9(&self) -> OSPEEDR_R {
157        OSPEEDR_R::new(((self.bits >> 18) & 3) as u8)
158    }
159    ///Bits 20:21 - Port x configuration pin 10
160    #[inline(always)]
161    pub fn ospeedr10(&self) -> OSPEEDR_R {
162        OSPEEDR_R::new(((self.bits >> 20) & 3) as u8)
163    }
164    ///Bits 22:23 - Port x configuration pin 11
165    #[inline(always)]
166    pub fn ospeedr11(&self) -> OSPEEDR_R {
167        OSPEEDR_R::new(((self.bits >> 22) & 3) as u8)
168    }
169    ///Bits 24:25 - Port x configuration pin 12
170    #[inline(always)]
171    pub fn ospeedr12(&self) -> OSPEEDR_R {
172        OSPEEDR_R::new(((self.bits >> 24) & 3) as u8)
173    }
174    ///Bits 26:27 - Port x configuration pin 13
175    #[inline(always)]
176    pub fn ospeedr13(&self) -> OSPEEDR_R {
177        OSPEEDR_R::new(((self.bits >> 26) & 3) as u8)
178    }
179    ///Bits 28:29 - Port x configuration pin 14
180    #[inline(always)]
181    pub fn ospeedr14(&self) -> OSPEEDR_R {
182        OSPEEDR_R::new(((self.bits >> 28) & 3) as u8)
183    }
184    ///Bits 30:31 - Port x configuration pin 15
185    #[inline(always)]
186    pub fn ospeedr15(&self) -> OSPEEDR_R {
187        OSPEEDR_R::new(((self.bits >> 30) & 3) as u8)
188    }
189}
190impl core::fmt::Debug for R {
191    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
192        f.debug_struct("OSPEEDR")
193            .field("ospeedr0", &self.ospeedr0())
194            .field("ospeedr1", &self.ospeedr1())
195            .field("ospeedr2", &self.ospeedr2())
196            .field("ospeedr3", &self.ospeedr3())
197            .field("ospeedr4", &self.ospeedr4())
198            .field("ospeedr5", &self.ospeedr5())
199            .field("ospeedr6", &self.ospeedr6())
200            .field("ospeedr7", &self.ospeedr7())
201            .field("ospeedr8", &self.ospeedr8())
202            .field("ospeedr9", &self.ospeedr9())
203            .field("ospeedr10", &self.ospeedr10())
204            .field("ospeedr11", &self.ospeedr11())
205            .field("ospeedr12", &self.ospeedr12())
206            .field("ospeedr13", &self.ospeedr13())
207            .field("ospeedr14", &self.ospeedr14())
208            .field("ospeedr15", &self.ospeedr15())
209            .finish()
210    }
211}
212impl W {
213    ///Port x configuration pin (0-15)
214    ///
215    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OSPEEDR0` field.</div>
216    #[inline(always)]
217    pub fn ospeedr(&mut self, n: u8) -> OSPEEDR_W<OSPEEDRrs> {
218        #[allow(clippy::no_effect)] [(); 16][n as usize];
219        OSPEEDR_W::new(self, n * 2)
220    }
221    ///Bits 0:1 - Port x configuration pin 0
222    #[inline(always)]
223    pub fn ospeedr0(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
224        OSPEEDR_W::new(self, 0)
225    }
226    ///Bits 2:3 - Port x configuration pin 1
227    #[inline(always)]
228    pub fn ospeedr1(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
229        OSPEEDR_W::new(self, 2)
230    }
231    ///Bits 4:5 - Port x configuration pin 2
232    #[inline(always)]
233    pub fn ospeedr2(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
234        OSPEEDR_W::new(self, 4)
235    }
236    ///Bits 6:7 - Port x configuration pin 3
237    #[inline(always)]
238    pub fn ospeedr3(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
239        OSPEEDR_W::new(self, 6)
240    }
241    ///Bits 8:9 - Port x configuration pin 4
242    #[inline(always)]
243    pub fn ospeedr4(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
244        OSPEEDR_W::new(self, 8)
245    }
246    ///Bits 10:11 - Port x configuration pin 5
247    #[inline(always)]
248    pub fn ospeedr5(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
249        OSPEEDR_W::new(self, 10)
250    }
251    ///Bits 12:13 - Port x configuration pin 6
252    #[inline(always)]
253    pub fn ospeedr6(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
254        OSPEEDR_W::new(self, 12)
255    }
256    ///Bits 14:15 - Port x configuration pin 7
257    #[inline(always)]
258    pub fn ospeedr7(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
259        OSPEEDR_W::new(self, 14)
260    }
261    ///Bits 16:17 - Port x configuration pin 8
262    #[inline(always)]
263    pub fn ospeedr8(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
264        OSPEEDR_W::new(self, 16)
265    }
266    ///Bits 18:19 - Port x configuration pin 9
267    #[inline(always)]
268    pub fn ospeedr9(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
269        OSPEEDR_W::new(self, 18)
270    }
271    ///Bits 20:21 - Port x configuration pin 10
272    #[inline(always)]
273    pub fn ospeedr10(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
274        OSPEEDR_W::new(self, 20)
275    }
276    ///Bits 22:23 - Port x configuration pin 11
277    #[inline(always)]
278    pub fn ospeedr11(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
279        OSPEEDR_W::new(self, 22)
280    }
281    ///Bits 24:25 - Port x configuration pin 12
282    #[inline(always)]
283    pub fn ospeedr12(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
284        OSPEEDR_W::new(self, 24)
285    }
286    ///Bits 26:27 - Port x configuration pin 13
287    #[inline(always)]
288    pub fn ospeedr13(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
289        OSPEEDR_W::new(self, 26)
290    }
291    ///Bits 28:29 - Port x configuration pin 14
292    #[inline(always)]
293    pub fn ospeedr14(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
294        OSPEEDR_W::new(self, 28)
295    }
296    ///Bits 30:31 - Port x configuration pin 15
297    #[inline(always)]
298    pub fn ospeedr15(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
299        OSPEEDR_W::new(self, 30)
300    }
301}
302/**GPIO port output speed register
303
304You can [`read`](crate::Reg::read) this register and get [`ospeedr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ospeedr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
305
306See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#GPIOB:OSPEEDR)*/
307pub struct OSPEEDRrs;
308impl crate::RegisterSpec for OSPEEDRrs {
309    type Ux = u32;
310}
311///`read()` method returns [`ospeedr::R`](R) reader structure
312impl crate::Readable for OSPEEDRrs {}
313///`write(|w| ..)` method takes [`ospeedr::W`](W) writer structure
314impl crate::Writable for OSPEEDRrs {
315    type Safety = crate::Unsafe;
316    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
317    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
318}
319///`reset()` method sets OSPEEDR to value 0
320impl crate::Resettable for OSPEEDRrs {
321    const RESET_VALUE: u32 = 0;
322}
stm32g0_staging/stm32g030/gpiob/ospeedr.rs

stm32g0_staging/stm32g030/gpiob/
ospeedr.rs
