stm32g0_staging/stm32g030/
exti.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    rtsr1: RTSR1,
6    ftsr1: FTSR1,
7    swier1: SWIER1,
8    rpr1: RPR1,
9    fpr1: FPR1,
10    _reserved5: [u8; 0x4c],
11    exticr1: EXTICR1,
12    exticr2: EXTICR2,
13    exticr3: EXTICR3,
14    exticr4: EXTICR4,
15    _reserved9: [u8; 0x10],
16    imr1: IMR1,
17    emr1: EMR1,
18}
19impl RegisterBlock {
20    ///0x00 - EXTI rising trigger selection register
21    #[inline(always)]
22    pub const fn rtsr1(&self) -> &RTSR1 {
23        &self.rtsr1
24    }
25    ///0x04 - EXTI falling trigger selection register
26    #[inline(always)]
27    pub const fn ftsr1(&self) -> &FTSR1 {
28        &self.ftsr1
29    }
30    ///0x08 - EXTI software interrupt event register
31    #[inline(always)]
32    pub const fn swier1(&self) -> &SWIER1 {
33        &self.swier1
34    }
35    ///0x0c - EXTI rising edge pending register
36    #[inline(always)]
37    pub const fn rpr1(&self) -> &RPR1 {
38        &self.rpr1
39    }
40    ///0x10 - EXTI falling edge pending register
41    #[inline(always)]
42    pub const fn fpr1(&self) -> &FPR1 {
43        &self.fpr1
44    }
45    ///0x60 - EXTI external interrupt selection register
46    #[inline(always)]
47    pub const fn exticr1(&self) -> &EXTICR1 {
48        &self.exticr1
49    }
50    ///0x64 - EXTI external interrupt selection register
51    #[inline(always)]
52    pub const fn exticr2(&self) -> &EXTICR2 {
53        &self.exticr2
54    }
55    ///0x68 - EXTI external interrupt selection register
56    #[inline(always)]
57    pub const fn exticr3(&self) -> &EXTICR3 {
58        &self.exticr3
59    }
60    ///0x6c - EXTI external interrupt selection register
61    #[inline(always)]
62    pub const fn exticr4(&self) -> &EXTICR4 {
63        &self.exticr4
64    }
65    ///0x80 - EXTI CPU wakeup with interrupt mask register
66    #[inline(always)]
67    pub const fn imr1(&self) -> &IMR1 {
68        &self.imr1
69    }
70    ///0x84 - EXTI CPU wakeup with event mask register
71    #[inline(always)]
72    pub const fn emr1(&self) -> &EMR1 {
73        &self.emr1
74    }
75}
76/**RTSR1 (rw) register accessor: EXTI rising trigger selection register
77
78You can [`read`](crate::Reg::read) this register and get [`rtsr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtsr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
79
80See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:RTSR1)
81
82For information about available fields see [`mod@rtsr1`]
83module*/
84pub type RTSR1 = crate::Reg<rtsr1::RTSR1rs>;
85///EXTI rising trigger selection register
86pub mod rtsr1;
87/**FTSR1 (rw) register accessor: EXTI falling trigger selection register
88
89You can [`read`](crate::Reg::read) this register and get [`ftsr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ftsr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
90
91See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:FTSR1)
92
93For information about available fields see [`mod@ftsr1`]
94module*/
95pub type FTSR1 = crate::Reg<ftsr1::FTSR1rs>;
96///EXTI falling trigger selection register
97pub mod ftsr1;
98/**SWIER1 (rw) register accessor: EXTI software interrupt event register
99
100You can [`read`](crate::Reg::read) this register and get [`swier1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swier1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
101
102See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:SWIER1)
103
104For information about available fields see [`mod@swier1`]
105module*/
106pub type SWIER1 = crate::Reg<swier1::SWIER1rs>;
107///EXTI software interrupt event register
108pub mod swier1;
109/**RPR1 (rw) register accessor: EXTI rising edge pending register
110
111You can [`read`](crate::Reg::read) this register and get [`rpr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rpr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
112
113See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:RPR1)
114
115For information about available fields see [`mod@rpr1`]
116module*/
117pub type RPR1 = crate::Reg<rpr1::RPR1rs>;
118///EXTI rising edge pending register
119pub mod rpr1;
120/**FPR1 (rw) register accessor: EXTI falling edge pending register
121
122You can [`read`](crate::Reg::read) this register and get [`fpr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fpr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
123
124See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:FPR1)
125
126For information about available fields see [`mod@fpr1`]
127module*/
128pub type FPR1 = crate::Reg<fpr1::FPR1rs>;
129///EXTI falling edge pending register
130pub mod fpr1;
131/**EXTICR1 (rw) register accessor: EXTI external interrupt selection register
132
133You can [`read`](crate::Reg::read) this register and get [`exticr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
134
135See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:EXTICR1)
136
137For information about available fields see [`mod@exticr1`]
138module*/
139pub type EXTICR1 = crate::Reg<exticr1::EXTICR1rs>;
140///EXTI external interrupt selection register
141pub mod exticr1;
142/**EXTICR2 (rw) register accessor: EXTI external interrupt selection register
143
144You can [`read`](crate::Reg::read) this register and get [`exticr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
145
146See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:EXTICR2)
147
148For information about available fields see [`mod@exticr2`]
149module*/
150pub type EXTICR2 = crate::Reg<exticr2::EXTICR2rs>;
151///EXTI external interrupt selection register
152pub mod exticr2;
153/**EXTICR3 (rw) register accessor: EXTI external interrupt selection register
154
155You can [`read`](crate::Reg::read) this register and get [`exticr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
156
157See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:EXTICR3)
158
159For information about available fields see [`mod@exticr3`]
160module*/
161pub type EXTICR3 = crate::Reg<exticr3::EXTICR3rs>;
162///EXTI external interrupt selection register
163pub mod exticr3;
164/**EXTICR4 (rw) register accessor: EXTI external interrupt selection register
165
166You can [`read`](crate::Reg::read) this register and get [`exticr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`exticr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:EXTICR4)
169
170For information about available fields see [`mod@exticr4`]
171module*/
172pub type EXTICR4 = crate::Reg<exticr4::EXTICR4rs>;
173///EXTI external interrupt selection register
174pub mod exticr4;
175/**IMR1 (rw) register accessor: EXTI CPU wakeup with interrupt mask register
176
177You can [`read`](crate::Reg::read) this register and get [`imr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
178
179See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:IMR1)
180
181For information about available fields see [`mod@imr1`]
182module*/
183pub type IMR1 = crate::Reg<imr1::IMR1rs>;
184///EXTI CPU wakeup with interrupt mask register
185pub mod imr1;
186/**EMR1 (rw) register accessor: EXTI CPU wakeup with event mask register
187
188You can [`read`](crate::Reg::read) this register and get [`emr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
189
190See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G030.html#EXTI:EMR1)
191
192For information about available fields see [`mod@emr1`]
193module*/
194pub type EMR1 = crate::Reg<emr1::EMR1rs>;
195///EXTI CPU wakeup with event mask register
196pub mod emr1;
stm32g0_staging/stm32g030/exti.rs

stm32g0_staging/stm32g030/
exti.rs
