stm32g0_staging/stm32g0c1/tim2/
tisel.rs

1///Register `TISEL` reader
2pub type R = crate::R<TISELrs>;
3///Register `TISEL` writer
4pub type W = crate::W<TISELrs>;
5/**Field `TI1SEL` reader - TI1\[0\]
6to TI1\[15\]
7input selection These bits select the TI1\[0\]
8to TI1\[15\]
9input source. Others: Reserved*/
10pub type TI1SEL_R = crate::FieldReader;
11/**Field `TI1SEL` writer - TI1\[0\]
12to TI1\[15\]
13input selection These bits select the TI1\[0\]
14to TI1\[15\]
15input source. Others: Reserved*/
16pub type TI1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17/**Field `TI2SEL` reader - TI2\[0\]
18to TI2\[15\]
19input selection These bits select the TI2\[0\]
20to TI2\[15\]
21input source. Others: Reserved*/
22pub type TI2SEL_R = crate::FieldReader;
23/**Field `TI2SEL` writer - TI2\[0\]
24to TI2\[15\]
25input selection These bits select the TI2\[0\]
26to TI2\[15\]
27input source. Others: Reserved*/
28pub type TI2SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29impl R {
30    /**Bits 0:3 - TI1\[0\]
31to TI1\[15\]
32input selection These bits select the TI1\[0\]
33to TI1\[15\]
34input source. Others: Reserved*/
35    #[inline(always)]
36    pub fn ti1sel(&self) -> TI1SEL_R {
37        TI1SEL_R::new((self.bits & 0x0f) as u8)
38    }
39    /**Bits 8:11 - TI2\[0\]
40to TI2\[15\]
41input selection These bits select the TI2\[0\]
42to TI2\[15\]
43input source. Others: Reserved*/
44    #[inline(always)]
45    pub fn ti2sel(&self) -> TI2SEL_R {
46        TI2SEL_R::new(((self.bits >> 8) & 0x0f) as u8)
47    }
48}
49impl core::fmt::Debug for R {
50    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
51        f.debug_struct("TISEL")
52            .field("ti1sel", &self.ti1sel())
53            .field("ti2sel", &self.ti2sel())
54            .finish()
55    }
56}
57impl W {
58    /**Bits 0:3 - TI1\[0\]
59to TI1\[15\]
60input selection These bits select the TI1\[0\]
61to TI1\[15\]
62input source. Others: Reserved*/
63    #[inline(always)]
64    pub fn ti1sel(&mut self) -> TI1SEL_W<TISELrs> {
65        TI1SEL_W::new(self, 0)
66    }
67    /**Bits 8:11 - TI2\[0\]
68to TI2\[15\]
69input selection These bits select the TI2\[0\]
70to TI2\[15\]
71input source. Others: Reserved*/
72    #[inline(always)]
73    pub fn ti2sel(&mut self) -> TI2SEL_W<TISELrs> {
74        TI2SEL_W::new(self, 8)
75    }
76}
77/**TIM alternate function option register 1
78
79You can [`read`](crate::Reg::read) this register and get [`tisel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
80
81See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0C1.html#TIM2:TISEL)*/
82pub struct TISELrs;
83impl crate::RegisterSpec for TISELrs {
84    type Ux = u32;
85}
86///`read()` method returns [`tisel::R`](R) reader structure
87impl crate::Readable for TISELrs {}
88///`write(|w| ..)` method takes [`tisel::W`](W) writer structure
89impl crate::Writable for TISELrs {
90    type Safety = crate::Unsafe;
91    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
92    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
93}
94///`reset()` method sets TISEL to value 0
95impl crate::Resettable for TISELrs {
96    const RESET_VALUE: u32 = 0;
97}
stm32g0_staging/stm32g0c1/tim2/tisel.rs

stm32g0_staging/stm32g0c1/tim2/
tisel.rs
