stm32g0_staging/stm32g0b0/tim16/
tisel.rs

1///Register `TISEL` reader
2pub type R = crate::R<TISELrs>;
3///Register `TISEL` writer
4pub type W = crate::W<TISELrs>;
5/**Field `TI1SEL` reader - selects TI1\[0\]
6to TI1\[15\]
7input Others: Reserved*/
8pub type TI1SEL_R = crate::FieldReader;
9/**Field `TI1SEL` writer - selects TI1\[0\]
10to TI1\[15\]
11input Others: Reserved*/
12pub type TI1SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14    /**Bits 0:3 - selects TI1\[0\]
15to TI1\[15\]
16input Others: Reserved*/
17    #[inline(always)]
18    pub fn ti1sel(&self) -> TI1SEL_R {
19        TI1SEL_R::new((self.bits & 0x0f) as u8)
20    }
21}
22impl core::fmt::Debug for R {
23    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
24        f.debug_struct("TISEL").field("ti1sel", &self.ti1sel()).finish()
25    }
26}
27impl W {
28    /**Bits 0:3 - selects TI1\[0\]
29to TI1\[15\]
30input Others: Reserved*/
31    #[inline(always)]
32    pub fn ti1sel(&mut self) -> TI1SEL_W<TISELrs> {
33        TI1SEL_W::new(self, 0)
34    }
35}
36/**input selection register
37
38You can [`read`](crate::Reg::read) this register and get [`tisel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tisel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
39
40See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#TIM16:TISEL)*/
41pub struct TISELrs;
42impl crate::RegisterSpec for TISELrs {
43    type Ux = u32;
44}
45///`read()` method returns [`tisel::R`](R) reader structure
46impl crate::Readable for TISELrs {}
47///`write(|w| ..)` method takes [`tisel::W`](W) writer structure
48impl crate::Writable for TISELrs {
49    type Safety = crate::Unsafe;
50    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
51    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
52}
53///`reset()` method sets TISEL to value 0
54impl crate::Resettable for TISELrs {
55    const RESET_VALUE: u32 = 0;
56}
stm32g0_staging/stm32g0b0/tim16/tisel.rs

stm32g0_staging/stm32g0b0/tim16/
tisel.rs
