stm32g0_staging/stm32g0b0/rtc/
prer.rs

1///Register `PRER` reader
2pub type R = crate::R<PRERrs>;
3///Register `PRER` writer
4pub type W = crate::W<PRERrs>;
5///Field `PREDIV_S` reader - Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
6pub type PREDIV_S_R = crate::FieldReader<u16>;
7///Field `PREDIV_S` writer - Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
8pub type PREDIV_S_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16, crate::Safe>;
9///Field `PREDIV_A` reader - Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
10pub type PREDIV_A_R = crate::FieldReader;
11///Field `PREDIV_A` writer - Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
12pub type PREDIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
13impl R {
14    ///Bits 0:14 - Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
15    #[inline(always)]
16    pub fn prediv_s(&self) -> PREDIV_S_R {
17        PREDIV_S_R::new((self.bits & 0x7fff) as u16)
18    }
19    ///Bits 16:22 - Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
20    #[inline(always)]
21    pub fn prediv_a(&self) -> PREDIV_A_R {
22        PREDIV_A_R::new(((self.bits >> 16) & 0x7f) as u8)
23    }
24}
25impl core::fmt::Debug for R {
26    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27        f.debug_struct("PRER")
28            .field("prediv_s", &self.prediv_s())
29            .field("prediv_a", &self.prediv_a())
30            .finish()
31    }
32}
33impl W {
34    ///Bits 0:14 - Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
35    #[inline(always)]
36    pub fn prediv_s(&mut self) -> PREDIV_S_W<PRERrs> {
37        PREDIV_S_W::new(self, 0)
38    }
39    ///Bits 16:22 - Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
40    #[inline(always)]
41    pub fn prediv_a(&mut self) -> PREDIV_A_W<PRERrs> {
42        PREDIV_A_W::new(self, 16)
43    }
44}
45/**RTC prescaler register
46
47You can [`read`](crate::Reg::read) this register and get [`prer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
48
49See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RTC:PRER)*/
50pub struct PRERrs;
51impl crate::RegisterSpec for PRERrs {
52    type Ux = u32;
53}
54///`read()` method returns [`prer::R`](R) reader structure
55impl crate::Readable for PRERrs {}
56///`write(|w| ..)` method takes [`prer::W`](W) writer structure
57impl crate::Writable for PRERrs {
58    type Safety = crate::Unsafe;
59    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
60    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
61}
62///`reset()` method sets PRER to value 0x007f_00ff
63impl crate::Resettable for PRERrs {
64    const RESET_VALUE: u32 = 0x007f_00ff;
65}
stm32g0_staging/stm32g0b0/rtc/prer.rs

stm32g0_staging/stm32g0b0/rtc/
prer.rs
