Struct stm32f7xx_hal::pac::tim5::ccmr2_output::OC4M_W

pub struct OC4M_W<'a> { /* private fields */ }

Field OC4M writer - OC4M

Implementations

impl<'a> OC4M_W<'a>

pub fn variant(self, variant: OC3M_A) -> &'a mut W

Writes variant to the field

pub fn frozen(self) -> &'a mut W

The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive

pub fn active_on_match(self) -> &'a mut W

Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1

pub fn inactive_on_match(self) -> &'a mut W

Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved

pub fn toggle(self) -> &'a mut W

OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved

pub fn force_inactive(self) -> &'a mut W

OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF

pub fn force_active(self) -> &'a mut W

OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF

pub fn pwm_mode1(self) -> &'a mut W

In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down

pub fn pwm_mode2(self) -> &'a mut W

Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

pub fn bits(self, value: u8) -> &'a mut W

Writes raw bits to the field