stm32f7xx_hal/timer/
pins.rs

1use crate::gpio::{self, Alternate};
2
3// Output channels markers
4pub trait CPin<TIM, const C: u8> {}
5pub struct Ch<const C: u8>;
6pub const C1: u8 = 0;
7pub const C2: u8 = 1;
8pub const C3: u8 = 2;
9pub const C4: u8 = 3;
10
11macro_rules! channel_impl {
12    ( $( $TIM:ident, $C:ident, $PINX:ident, $AF:literal; )+ ) => {
13        $(
14            impl<Otype> CPin<crate::pac::$TIM, $C> for gpio::$PINX<Alternate<$AF, Otype>> { }
15        )+
16    };
17}
18
19// The approach to PWM channel implementation is to group parts with
20// common pins, starting with groupings of the largest number of parts
21// and moving to smaller and smaller groupings.  Last, we have individual
22// parts to cover exceptions.
23
24// All parts have these PWM pins.
25channel_impl!(
26    TIM1, C1, PA8, 1;
27    TIM1, C2, PA9, 1;
28    TIM1, C3, PA10, 1;
29    TIM1, C4, PA11, 1;
30
31    TIM5, C1, PA0, 2;
32    TIM5, C2, PA1, 2;
33    TIM5, C3, PA2, 2;
34    TIM5, C4, PA3, 2;
35
36    TIM9, C1, PA2, 3;
37    TIM9, C2, PA3, 3;
38
39    TIM11, C1, PB9, 3;
40);
41
42// TODO: check for other groups of parts
43channel_impl!(
44    TIM1, C1, PE9, 1;
45    TIM1, C2, PE11, 1;
46    TIM1, C3, PE13, 1;
47    TIM1, C4, PE14, 1;
48
49    TIM2, C1, PA0, 1;
50    TIM2, C2, PA1, 1;
51    TIM2, C3, PA2, 1;
52    TIM2, C4, PA3, 1;
53
54    TIM2, C2, PB3, 1;
55    TIM2, C3, PB10, 1;
56    TIM2, C4, PB11, 1;
57
58    TIM2, C1, PA5, 1;
59    TIM2, C1, PA15, 1;
60
61    TIM3, C1, PA6, 2;
62    TIM3, C2, PA7, 2;
63    TIM3, C3, PB0, 2;
64    TIM3, C4, PB1, 2;
65
66    TIM3, C1, PB4, 2;
67    TIM3, C2, PB5, 2;
68
69    TIM3, C1, PC6, 2;
70    TIM3, C2, PC7, 2;
71    TIM3, C3, PC8, 2;
72    TIM3, C4, PC9, 2;
73
74    TIM4, C1, PB6, 2;
75    TIM4, C2, PB7, 2;
76    TIM4, C3, PB8, 2;
77    TIM4, C4, PB9, 2;
78
79    TIM4, C1, PD12, 2;
80    TIM4, C2, PD13, 2;
81    TIM4, C3, PD14, 2;
82    TIM4, C4, PD15, 2;
83
84    TIM10, C1, PB8, 3;
85);
86
87channel_impl!(
88    TIM9, C1, PE5, 3;
89    TIM9, C2, PE6, 3;
90);
91
92channel_impl!(
93    TIM8, C1, PC6, 3;
94    TIM8, C2, PC7, 3;
95    TIM8, C3, PC8, 3;
96    TIM8, C4, PC9, 3;
97
98    TIM10, C1, PF6, 3;
99
100    TIM11, C1, PF7, 3;
101
102    TIM12, C1, PB14, 9;
103    TIM12, C2, PB15, 9;
104
105    TIM13, C1, PA6, 9;
106    TIM13, C1, PF8, 9;  // Not a mistake: TIM13 has only one channel.
107
108    TIM14, C1, PA7, 9;
109    TIM14, C1, PF9, 9;  // Not a mistake: TIM14 has only one channel.
110);
111
112channel_impl!(
113    TIM5, C1, PH10, 2;
114    TIM5, C2, PH11, 2;
115    TIM5, C3, PH12, 2;
116    TIM5, C4, PI0, 2;
117
118    TIM8, C1, PI5, 3;
119    TIM8, C2, PI6, 3;
120    TIM8, C3, PI7, 3;
121    TIM8, C4, PI2, 3;
122
123    TIM12, C1, PH6, 9;
124    TIM12, C2, PH9, 9;
125);
stm32f7xx_hal/timer/pins.rs

stm32f7xx_hal/timer/
pins.rs
