stm32f7xx_hal/rcc/
enable.rs

1use super::*;
2
3macro_rules! bus_enable {
4    ($PER:ident => $en:ident) => {
5        impl Enable for crate::pac::$PER {
6            #[inline(always)]
7            fn enable(bus: &mut Self::Bus) {
8                bus.enr().modify(|_, w| w.$en().set_bit());
9                // Stall the pipeline to work around erratum 2.1.13 (DM00037591)
10                cortex_m::asm::dsb();
11            }
12            #[inline(always)]
13            fn disable(bus: &mut Self::Bus) {
14                bus.enr().modify(|_, w| w.$en().clear_bit());
15            }
16            #[inline(always)]
17            fn is_enabled() -> bool {
18                Self::Bus::new().enr().read().$en().bit_is_set()
19            }
20            #[inline(always)]
21            fn is_disabled() -> bool {
22                Self::Bus::new().enr().read().$en().bit_is_clear()
23            }
24            #[inline(always)]
25            unsafe fn enable_unchecked() {
26                Self::enable(&mut Self::Bus::new());
27            }
28            #[inline(always)]
29            unsafe fn disable_unchecked() {
30                Self::disable(&mut Self::Bus::new());
31            }
32        }
33    };
34}
35
36macro_rules! bus_lpenable {
37    ($PER:ident => $lpen:ident) => {
38        impl LPEnable for crate::pac::$PER {
39            #[inline(always)]
40            fn low_power_enable(bus: &mut Self::Bus) {
41                bus.lpenr().modify(|_, w| w.$lpen().set_bit());
42                // Stall the pipeline to work around erratum 2.1.13 (DM00037591)
43                cortex_m::asm::dsb();
44            }
45            #[inline(always)]
46            fn low_power_disable(bus: &mut Self::Bus) {
47                bus.lpenr().modify(|_, w| w.$lpen().clear_bit());
48            }
49            #[inline(always)]
50            fn is_low_power_enabled() -> bool {
51                Self::Bus::new().lpenr().read().$lpen().bit_is_set()
52            }
53            #[inline(always)]
54            fn is_low_power_disabled() -> bool {
55                Self::Bus::new().lpenr().read().$lpen().bit_is_clear()
56            }
57            #[inline(always)]
58            unsafe fn low_power_enable_unchecked() {
59                Self::enable(&mut Self::Bus::new());
60            }
61            #[inline(always)]
62            unsafe fn low_power_disable_unchecked() {
63                Self::disable(&mut Self::Bus::new());
64            }
65        }
66    };
67}
68macro_rules! bus_reset {
69    ($PER:ident => $rst:ident) => {
70        impl Reset for crate::pac::$PER {
71            #[inline(always)]
72            fn reset(bus: &mut Self::Bus) {
73                bus.rstr().modify(|_, w| w.$rst().set_bit());
74                bus.rstr().modify(|_, w| w.$rst().clear_bit());
75            }
76            #[inline(always)]
77            unsafe fn reset_unchecked() {
78                Self::reset(&mut Self::Bus::new());
79            }
80        }
81    };
82}
83
84macro_rules! bus {
85    ($($PER:ident => ($busX:ty, $($en:ident)?, $($lpen:ident)?, $($rst:ident)?),)+) => {
86        $(
87            impl crate::Sealed for crate::pac::$PER {}
88            impl RccBus for crate::pac::$PER {
89                type Bus = $busX;
90            }
91            $(bus_enable!($PER => $en);)?
92            $(bus_lpenable!($PER => $lpen);)?
93            $(bus_reset!($PER => $rst);)?
94        )+
95    };
96}
97
98// Peripherals respective buses
99// TODO: check which processor has which peripheral and add them
100bus! {
101    GPIOA => (AHB1, gpioaen, gpioalpen, gpioarst), // 0
102    GPIOB => (AHB1, gpioben, gpioblpen, gpiobrst), // 1
103    GPIOC => (AHB1, gpiocen, gpioclpen, gpiocrst), // 2
104    GPIOD => (AHB1, gpioden, gpiodlpen, gpiodrst), // 3
105    GPIOE => (AHB1, gpioeen, gpioelpen, gpioerst), // 4
106    GPIOF => (AHB1, gpiofen, gpioflpen, gpiofrst), // 5
107    GPIOG => (AHB1, gpiogen, gpioglpen, gpiogrst), // 6
108    GPIOH => (AHB1, gpiohen, gpiohlpen, gpiohrst), // 7
109    GPIOI => (AHB1, gpioien, gpioilpen, gpioirst), // 8
110    CRC => (AHB1, crcen, crclpen, crcrst), // 12
111    DMA1 => (AHB1, dma1en, dma1lpen, dma1rst), // 21
112    DMA2 => (AHB1, dma2en, dma2lpen, dma2rst), // 22
113    OTG_HS_GLOBAL => (AHB1, otghsen, otghslpen, otghsrst), // 29
114
115    RNG => (AHB2, rngen, rnglpen, rngrst), // 6
116    OTG_FS_GLOBAL => (AHB2, otgfsen, otgfslpen, otgfsrst), // 7
117
118    FMC => (AHB3, fmcen, fmclpen, fmcrst), // 0
119    QUADSPI => (AHB3, qspien, qspilpen, qspirst), // 1
120
121    TIM2 => (APB1, tim2en, tim2lpen, tim2rst), // 0
122    TIM3 => (APB1, tim3en, tim3lpen, tim3rst), // 1
123    TIM4 => (APB1, tim4en, tim4lpen, tim4rst), // 2
124    TIM5 => (APB1, tim5en, tim5lpen, tim5rst), // 3
125    TIM6 => (APB1, tim6en, tim6lpen, tim6rst), // 4
126    TIM7 => (APB1, tim7en, tim7lpen, tim7rst), // 5
127    TIM12 => (APB1, tim12en, tim12lpen, tim12rst), // 6
128    TIM13 => (APB1, tim13en, tim13lpen, tim13rst), // 7
129    TIM14 => (APB1, tim14en, tim14lpen, tim14rst), // 8
130    LPTIM1 => (APB1, lptim1en, lptim1lpen, lptim1rst), // 9
131    WWDG => (APB1, wwdgen, wwdglpen, wwdgrst), // 11
132    SPI2 => (APB1, spi2en, spi2lpen, spi2rst), // 14
133    SPI3 => (APB1, spi3en, spi3lpen, spi3rst), // 15
134    USART2 => (APB1, usart2en, usart2lpen, usart2rst), // 17
135    USART3 => (APB1, usart3en, usart3lpen, usart3rst), // 18
136    UART4 => (APB1, uart4en, uart4lpen, uart4rst), // 19
137    UART5 => (APB1, uart5en, uart5lpen, uart5rst), // 20
138    I2C1 => (APB1, i2c1en, i2c1lpen, i2c1rst), // 21
139    I2C2 => (APB1, i2c2en, i2c2lpen, i2c2rst), // 22
140    I2C3 => (APB1, i2c3en, i2c3lpen, i2c3rst), // 23
141    CAN1 => (APB1, can1en, can1lpen, can1rst), // 25
142    PWR => (APB1, pwren, pwrlpen, pwrrst), // 28
143    DAC => (APB1, dacen, daclpen, dacrst), // 29
144    UART7 => (APB1, uart7en, uart7lpen, uart7rst), // 30
145    UART8 => (APB1, uart8en, uart8lpen, uart8rst), // 31
146
147    TIM1 => (APB2, tim1en, tim1lpen, tim1rst), // 0
148    TIM8 => (APB2, tim8en, tim8lpen, tim8rst), // 1
149    USART1 => (APB2, usart1en, usart1lpen, usart1rst), // 4
150    USART6 => (APB2, usart6en, usart6lpen, usart6rst), // 5
151    ADC1 => (APB2, adc1en, adc1lpen, adcrst), // 8
152    ADC2 => (APB2, adc2en, adc2lpen, adcrst), // 9
153    ADC3 => (APB2, adc3en, adc3lpen, adcrst), // 10
154    SDMMC1 => (APB2, sdmmc1en, sdmmc1lpen, sdmmc1rst), // 11
155    SPI1 => (APB2, spi1en, spi1lpen, spi1rst), // 12
156    SPI4 => (APB2, spi4en, spi4lpen, spi4rst), // 13
157    SYSCFG => (APB2, syscfgen, syscfglpen, syscfgrst), // 14
158    TIM9 => (APB2, tim9en, tim9lpen, tim9rst), // 16
159    TIM10 => (APB2, tim10en, tim10lpen, tim10rst), // 17
160    TIM11 => (APB2, tim11en, tim11lpen, tim11rst), // 18
161    SPI5 => (APB2, spi5en, spi5lpen, spi5rst), // 20
162    SAI1 => (APB2, sai1en, sai1lpen, sai1rst), // 22
163    SAI2 => (APB2, sai2en, sai2lpen, sai2rst), // 23
164}
165
166#[cfg(any(feature = "svd-f730", feature = "svd-f7x2", feature = "svd-f7x3",))]
167bus! {
168    AES => (AHB2, aesen, aeslpen, aesrst), // 4
169
170    SDMMC2 => (APB2, sdmmc2en, sdmmc2lpen, sdmmc2rst), // 7
171    USBPHYC => (APB2, usbphycen,, usbphycrst), // 31
172}
173
174#[cfg(any(
175    feature = "svd-f745",
176    feature = "svd-f750",
177    feature = "svd-f7x6",
178    feature = "svd-f765",
179    feature = "svd-f7x7",
180    feature = "svd-f7x9",
181))]
182bus! {
183    GPIOJ => (AHB1, gpiojen, gpiojlpen, gpiojrst), // 9
184    GPIOK => (AHB1, gpioken, gpioklpen, gpiokrst), // 10
185    DMA2D => (AHB1, dma2den, dma2dlpen, dma2drst), // 23
186    ETHERNET_MAC => (AHB1, ethmacen, ethmaclpen, ethmacrst), // 25
187
188    DCMI => (AHB2, dcmien, dcmilpen, dcmirst), // 0
189    CRYP => (AHB2, crypen, cryplpen, cryprst), // 4
190    HASH => (AHB2, hashen, hashlpen,), // 5
191
192    SPDIFRX => (APB1, spdifrxen, spdifrxlpen, spdifrxrst), // 16
193    I2C4 => (APB1, i2c4en, i2c4lpen, i2c4rst), // 24
194    CAN2 => (APB1, can2en, can2lpen, can2rst), // 26
195    CEC => (APB1, cecen, ceclpen, cecrst), // 27
196
197    SPI6 => (APB2, spi6en, spi6lpen, spi6rst), // 21
198    LTDC => (APB2, ltdcen, ltdclpen, ltdcrst), // 26
199}
200
201#[cfg(any(feature = "svd-f765", feature = "svd-f7x7", feature = "svd-f7x9"))]
202bus! {
203    JPEG => (AHB2, jpegen, jpeglpen,), // 1
204
205    CAN3 => (APB1, can3en, can3lpen, can3rst), // 13
206
207    DSI => (APB2, dsien, dsilpen, dsirst), // 27
208    MDIOS => (APB2, mdioen, mdiolpen, mdiorst), // 30
209}
210
211#[cfg(any(feature = "svd-f7x9", feature = "svd-f7x9"))]
212bus! {
213    DFSDM => (APB2, dfsdm1en, dfsdm1lpen, dfsdm1rst), // 29
214}
215
216#[cfg(feature = "svd-f765")]
217bus! {
218    DFSDM1 => (APB2, dfsdm1en, dfsdm1lpen, dfsdm1rst), // 29
219}
stm32f7xx_hal/rcc/enable.rs

stm32f7xx_hal/rcc/
enable.rs
