Enum stm32f7xx_hal::pac::rcc::dckcfgr1::PLLSAIDIVQ_A [−][src]
#[repr(u8)]
pub enum PLLSAIDIVQ_A {
Show 32 variants
DIV1,
DIV2,
DIV3,
DIV4,
DIV5,
DIV6,
DIV7,
DIV8,
DIV9,
DIV10,
DIV11,
DIV12,
DIV13,
DIV14,
DIV15,
DIV16,
DIV17,
DIV18,
DIV19,
DIV20,
DIV21,
DIV22,
DIV23,
DIV24,
DIV25,
DIV26,
DIV27,
DIV28,
DIV29,
DIV30,
DIV31,
DIV32,
}
Expand description
PLLSAI division factor for SAI1 clock
Value on reset: 16
Variants
0: PLLSAIDIVQ = /1
1: PLLSAIDIVQ = /2
2: PLLSAIDIVQ = /3
3: PLLSAIDIVQ = /4
4: PLLSAIDIVQ = /5
5: PLLSAIDIVQ = /6
6: PLLSAIDIVQ = /7
7: PLLSAIDIVQ = /8
8: PLLSAIDIVQ = /9
9: PLLSAIDIVQ = /10
10: PLLSAIDIVQ = /11
11: PLLSAIDIVQ = /12
12: PLLSAIDIVQ = /13
13: PLLSAIDIVQ = /14
14: PLLSAIDIVQ = /15
15: PLLSAIDIVQ = /16
16: PLLSAIDIVQ = /17
17: PLLSAIDIVQ = /18
18: PLLSAIDIVQ = /19
19: PLLSAIDIVQ = /20
20: PLLSAIDIVQ = /21
21: PLLSAIDIVQ = /22
22: PLLSAIDIVQ = /23
23: PLLSAIDIVQ = /24
24: PLLSAIDIVQ = /25
25: PLLSAIDIVQ = /26
26: PLLSAIDIVQ = /27
27: PLLSAIDIVQ = /28
28: PLLSAIDIVQ = /29
29: PLLSAIDIVQ = /30
30: PLLSAIDIVQ = /31
31: PLLSAIDIVQ = /32