Enum stm32f7xx_hal::pac::rcc::dckcfgr1::PLLI2SDIVQ_A [−][src]
#[repr(u8)]
pub enum PLLI2SDIVQ_A {
Show 32 variants
DIV1,
DIV2,
DIV3,
DIV4,
DIV5,
DIV6,
DIV7,
DIV8,
DIV9,
DIV10,
DIV11,
DIV12,
DIV13,
DIV14,
DIV15,
DIV16,
DIV17,
DIV18,
DIV19,
DIV20,
DIV21,
DIV22,
DIV23,
DIV24,
DIV25,
DIV26,
DIV27,
DIV28,
DIV29,
DIV30,
DIV31,
DIV32,
}
Expand description
PLLI2S division factor for SAI1 clock
Value on reset: 0
Variants
0: PLLI2SDIVQ = /1
1: PLLI2SDIVQ = /2
2: PLLI2SDIVQ = /3
3: PLLI2SDIVQ = /4
4: PLLI2SDIVQ = /5
5: PLLI2SDIVQ = /6
6: PLLI2SDIVQ = /7
7: PLLI2SDIVQ = /8
8: PLLI2SDIVQ = /9
9: PLLI2SDIVQ = /10
10: PLLI2SDIVQ = /11
11: PLLI2SDIVQ = /12
12: PLLI2SDIVQ = /13
13: PLLI2SDIVQ = /14
14: PLLI2SDIVQ = /15
15: PLLI2SDIVQ = /16
16: PLLI2SDIVQ = /17
17: PLLI2SDIVQ = /18
18: PLLI2SDIVQ = /19
19: PLLI2SDIVQ = /20
20: PLLI2SDIVQ = /21
21: PLLI2SDIVQ = /22
22: PLLI2SDIVQ = /23
23: PLLI2SDIVQ = /24
24: PLLI2SDIVQ = /25
25: PLLI2SDIVQ = /26
26: PLLI2SDIVQ = /27
27: PLLI2SDIVQ = /28
28: PLLI2SDIVQ = /29
29: PLLI2SDIVQ = /30
30: PLLI2SDIVQ = /31
31: PLLI2SDIVQ = /32