Struct stm32f7xx_hal::pac::dma2::ST [−][src]
#[repr(C)]pub struct ST {
pub cr: Reg<u32, _CR>,
pub ndtr: Reg<u32, _NDTR>,
pub par: Reg<u32, _PAR>,
pub m0ar: Reg<u32, _M0AR>,
pub m1ar: Reg<u32, _M1AR>,
pub fcr: Reg<u32, _FCR>,
}
Expand description
Register block
Fields
cr: Reg<u32, _CR>
0x00 - stream x configuration register
ndtr: Reg<u32, _NDTR>
0x04 - stream x number of data register
par: Reg<u32, _PAR>
0x08 - stream x peripheral address register
m0ar: Reg<u32, _M0AR>
0x0c - stream x memory 0 address register
m1ar: Reg<u32, _M1AR>
0x10 - stream x memory 1 address register
fcr: Reg<u32, _FCR>
0x14 - stream x FIFO control register