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//! # Quadrature Encoder Interface
use crate::hal::{self, Direction};
use crate::stm32::RCC;

use crate::gpio::gpioa::*;
use crate::gpio::gpiob::*;
use crate::gpio::gpioc::*;
use crate::gpio::gpiod::*;
use crate::gpio::gpioe::*;
use crate::gpio::gpiof::*;
use crate::gpio::gpioh::*;
use crate::gpio::gpioi::*;
use crate::gpio::{Alternate, AF1, AF2, AF3};

use crate::stm32::{TIM1, TIM5, TIM2, TIM3, TIM4, TIM8};

pub trait Pins<TIM> {}
pub trait PinC1<TIM> {}
pub trait PinC2<TIM> {}

impl<TIM, PC1, PC2> Pins<TIM> for (PC1, PC2)
where
    PC1: PinC1<TIM>,
    PC2: PinC2<TIM>,
{
}

impl PinC1<TIM1> for PA8<Alternate<AF1>> {}
impl PinC2<TIM1> for PA9<Alternate<AF1>> {}
impl PinC1<TIM1> for PE9<Alternate<AF1>> {}
impl PinC2<TIM1> for PE11<Alternate<AF1>> {}
impl PinC1<TIM2> for PA0<Alternate<AF1>> {}
impl PinC1<TIM2> for PA5<Alternate<AF1>> {}
impl PinC1<TIM2> for PA15<Alternate<AF1>> {}
impl PinC2<TIM2> for PA1<Alternate<AF1>> {}
impl PinC2<TIM2> for PB3<Alternate<AF1>> {}
impl PinC1<TIM2> for PB8<Alternate<AF1>> {}
impl PinC2<TIM2> for PB9<Alternate<AF1>> {}
impl PinC1<TIM3> for PA6<Alternate<AF2>> {}
impl PinC2<TIM3> for PA7<Alternate<AF2>> {}
impl PinC1<TIM3> for PB4<Alternate<AF2>> {}
impl PinC2<TIM3> for PB5<Alternate<AF2>> {}
impl PinC1<TIM3> for PC6<Alternate<AF2>> {}
impl PinC2<TIM3> for PC7<Alternate<AF2>> {}
impl PinC1<TIM4> for PB6<Alternate<AF2>> {}
impl PinC2<TIM4> for PB7<Alternate<AF2>> {}
impl PinC1<TIM4> for PD12<Alternate<AF2>> {}
impl PinC2<TIM4> for PD13<Alternate<AF2>> {}
impl PinC1<TIM5> for PA0<Alternate<AF2>> {}
impl PinC2<TIM5> for PA1<Alternate<AF2>> {}
impl PinC1<TIM5> for PB12<Alternate<AF2>> {}
impl PinC1<TIM5> for PF3<Alternate<AF2>> {}
impl PinC2<TIM5> for PF4<Alternate<AF2>> {}
impl PinC1<TIM5> for PH10<Alternate<AF2>> {}
impl PinC2<TIM5> for PH11<Alternate<AF2>> {}
impl PinC1<TIM8> for PC6<Alternate<AF3>> {}
impl PinC2<TIM8> for PC7<Alternate<AF3>> {}
impl PinC1<TIM8> for PI5<Alternate<AF3>> {}
impl PinC2<TIM8> for PI6<Alternate<AF3>> {}

/// Hardware quadrature encoder interface peripheral
pub struct Qei<TIM, PINS> {
    tim: TIM,
    pins: PINS,
}

macro_rules! hal {
    ($($TIM:ident: ($tim:ident, $timXen:ident, $timXrst:ident, $apbenr:ident, $apbrstr:ident, $bits:ident),)+) => {
        $(
            impl<PINS> Qei<$TIM, PINS> {
                /// Configures a TIM peripheral as a quadrature encoder interface input
                pub fn $tim(tim: $TIM, pins: PINS) -> Self
                where
                    PINS: Pins<$TIM>
                {
                    let rcc = unsafe { &(*RCC::ptr()) };
                    // enable and reset peripheral to a clean slate state
                    rcc.$apbenr.modify(|_, w| w.$timXen().set_bit());
                    rcc.$apbrstr.modify(|_, w| w.$timXrst().set_bit());
                    rcc.$apbrstr.modify(|_, w| w.$timXrst().clear_bit());

                    // Configure TxC1 and TxC2 as captures
                    tim.ccmr1_output
                        .write(|w| unsafe { w.cc1s().bits(0b01).cc2s().bits(0b01) });

                    // enable and configure to capture on rising edge
                    tim.ccer.write(|w| {
                        w.cc1e()
                            .set_bit()
                            .cc1p()
                            .clear_bit()
                            .cc2e()
                            .set_bit()
                            .cc2p()
                            .clear_bit()
                    });

                    // configure as quadrature encoder
                    // some chip variants declare `.bits()` as unsafe, some don't
                    #[allow(unused_unsafe)]
                    tim.smcr.write(|w| unsafe { w.sms().bits(3) });

                    tim.arr.write(|w| unsafe { w.bits(core::u32::MAX) });
                    tim.cr1.write(|w| w.cen().set_bit());

                    Qei { tim, pins }
                }

                /// Releases the TIM peripheral and QEI pins
                pub fn release(self) -> ($TIM, PINS) {
                    (self.tim, self.pins)
                }
            }

            impl<PINS> hal::Qei for Qei<$TIM, PINS> {
                type Count = $bits;

                fn count(&self) -> $bits {
                    self.tim.cnt.read().bits() as $bits
                }

                fn direction(&self) -> Direction {
                    if self.tim.cr1.read().dir().bit_is_clear() {
                        hal::Direction::Upcounting
                    } else {
                        hal::Direction::Downcounting
                    }
                }
            }

        )+
    }
}

hal! {
    TIM1: (tim1, tim1en, tim1rst, apb2enr, apb2rstr, u16),
    TIM5: (tim5, tim5en, tim5rst, apb1enr, apb1rstr, u32),
    TIM2: (tim2, tim2en, tim2rst, apb1enr, apb1rstr, u32),
    TIM3: (tim3, tim3en, tim3rst, apb1enr, apb1rstr, u16),
    TIM4: (tim4, tim4en, tim4rst, apb1enr, apb1rstr, u16),
    TIM8: (tim8, tim8en, tim8rst, apb2enr, apb2rstr, u16),
}