Struct stm32f7x6::rcc::pllcfgr::W
[−]
[src]
pub struct W { /* fields omitted */ }Value to write to the register
Methods
impl W[src]
pub fn reset_value() -> W[src]
Reset value of the register
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self[src]
Writes raw bits to the register
pub fn pllq3(&mut self) -> _PLLQ3W[src]
Bit 27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
pub fn pllq2(&mut self) -> _PLLQ2W[src]
Bit 26 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
pub fn pllq1(&mut self) -> _PLLQ1W[src]
Bit 25 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
pub fn pllq0(&mut self) -> _PLLQ0W[src]
Bit 24 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
pub fn pllsrc(&mut self) -> _PLLSRCW[src]
Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
pub fn pllp1(&mut self) -> _PLLP1W[src]
Bit 17 - Main PLL (PLL) division factor for main system clock
pub fn pllp0(&mut self) -> _PLLP0W[src]
Bit 16 - Main PLL (PLL) division factor for main system clock
pub fn plln8(&mut self) -> _PLLN8W[src]
Bit 14 - Main PLL (PLL) multiplication factor for VCO
pub fn plln7(&mut self) -> _PLLN7W[src]
Bit 13 - Main PLL (PLL) multiplication factor for VCO
pub fn plln6(&mut self) -> _PLLN6W[src]
Bit 12 - Main PLL (PLL) multiplication factor for VCO
pub fn plln5(&mut self) -> _PLLN5W[src]
Bit 11 - Main PLL (PLL) multiplication factor for VCO
pub fn plln4(&mut self) -> _PLLN4W[src]
Bit 10 - Main PLL (PLL) multiplication factor for VCO
pub fn plln3(&mut self) -> _PLLN3W[src]
Bit 9 - Main PLL (PLL) multiplication factor for VCO
pub fn plln2(&mut self) -> _PLLN2W[src]
Bit 8 - Main PLL (PLL) multiplication factor for VCO
pub fn plln1(&mut self) -> _PLLN1W[src]
Bit 7 - Main PLL (PLL) multiplication factor for VCO
pub fn plln0(&mut self) -> _PLLN0W[src]
Bit 6 - Main PLL (PLL) multiplication factor for VCO
pub fn pllm5(&mut self) -> _PLLM5W[src]
Bit 5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
pub fn pllm4(&mut self) -> _PLLM4W[src]
Bit 4 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
pub fn pllm3(&mut self) -> _PLLM3W[src]
Bit 3 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
pub fn pllm2(&mut self) -> _PLLM2W[src]
Bit 2 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
pub fn pllm1(&mut self) -> _PLLM1W[src]
Bit 1 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
pub fn pllm0(&mut self) -> _PLLM0W[src]
Bit 0 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock